System and method for MRAM having controlled averagable and isolatable voltage reference

• US 8,675,390 B2
• Filed: 10/21/2011
• Issued: 03/18/2014
• Est. Priority Date: 10/21/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Jung Pill, Kim, Taehyun
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US13/278,217
• Publication Number:
  US 20130100725A1
• Time in Patent Office: 879 Days
• Field of Search: 365/48, 365/66, 365/78, 365 80- 93, 365/100, 365/130, 365/131, 365/148, 365/158, 365/163, 365/171, 365/173, 365/225.5, 365/243.5, 257 2- 5, 257/296, 257/E31.047, 257/E27.006, 257/421, 257/E21.665, 438/29, 438/95, 438/96, 438/166, 438/259, 438/365, 438/482, 438/486, 438/597
• US Class Current: 365/148
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.

Claims

1. A Non-Volatile Resistive memory comprising:

a first array of bitcells (I/O) having a first voltage reference cell having a first voltage reference cell voltage output, a first voltage reference cell selectable link from the first voltage reference cell voltage output to a first I/O voltage reference line, and a first sense amplifier coupled to the first I/O voltage reference line, wherein the first voltage reference cell is configured to generate at the first reference cell voltage output a first reference voltage approximately midpoint between a given high read voltage and a given low read voltage;

a second I/O having a second voltage reference cell having a second voltage reference cell voltage output, a second voltage reference cell selectable link from the second voltage reference cell voltage output to a second I/O voltage reference line, and a second sense amplifier coupled to the second I/O voltage reference line, wherein the second voltage reference cell is configured to generate at the second voltage reference cell output a second reference voltage approximately midpoint between the given high read voltage and the given low read voltage; and

a voltage reference line coupling link between the first I/O voltage reference line and the second I/O voltage reference line.

2. The Non-Volatile Resistive memory of claim 1, wherein at least one of the first voltage reference cell selectable link and the second voltage reference cell selectable link is a fusible link capable of being blown to isolate at least one of the first voltage reference cell from the first I/O voltage reference line and the second voltage reference cell from the second I/O voltage reference line.

3. The Non-Volatile Resistive memory of claim 1, wherein at least one of the first voltage reference cell selectable link and the second voltage reference cell selectable link is a fusible link in a selected, blown state to isolate at least one of the first voltage reference cell from the first I/O voltage reference line and the second voltage reference cell from the second I/O voltage reference line.

4. The Non-Volatile Resistive memory of claim 1, wherein at least one of the first voltage reference cell selectable link and the second voltage reference cell selectable link is a switchable device capable of being switched to an on state coupling at least one of the first voltage reference cell to the first I/O voltage reference line and the second voltage reference cell to the second I/O voltage reference line, and capable of being switched to an off state to isolate at least one of the first voltage reference cell from the first I/O voltage reference line and the second voltage reference cell from the second I/O voltage reference line.

5. The Non-Volatile Resistive memory of claim 1, wherein the voltage reference line coupling link is a fusible link coupling the first I/O voltage reference line and the second I/O voltage reference line into a common voltage reference node coupled to the first sensing amplifier and to the second sending amplifier, said fusible link being capable of being blown to destroy the common voltage reference node.

6. The Non-Volatile Resistive memory of claim 5, wherein at least one of the first voltage reference cell selectable link and the second voltage reference cell selectable link is a fusible link capable of being blown to isolate at least one of the first voltage reference cell from the first I/O voltage reference line and the second voltage reference cell from the second I/O voltage reference line.

7. The Non-Volatile Resistive memory of claim 6, wherein at least one of the first voltage reference cell selectable link and the second voltage reference cell selectable link is a switchable device capable of being switched to an on state coupling at least one of the first voltage reference cell to the first I/O voltage reference line and the second voltage reference cell to the second I/O voltage reference line, and capable of being switched to an off state to isolate at least one of the first voltage reference cell from the first I/O reference line and the second voltage reference cell from the second I/O voltage reference line.

8. The Non-Volatile Resistive memory of claim 1, wherein the voltage reference line coupling link is a switchable device capable of being switched on to couple the first I/O voltage reference line and the second I/O voltage reference line into a common voltage reference node coupled to the first sensing amplifier and to the second sending amplifier and of being switched off to remove the common voltage reference node.

9. The Non-Volatile Resistive memory of claim 8, wherein at least one of the first voltage reference cell selectable link and the second voltage reference cell selectable link is a fusible link capable of being blown to isolate at least one of the first voltage reference cell from the first I/O voltage reference line and the second voltage reference cell from the second I/O voltage reference line.

10. The Non-Volatile Resistive memory of claim 8, wherein at least one of the first voltage reference cell selectable link and the second voltage reference cell selectable link is a switchable device capable of being switched to an on state coupling at least one of the first voltage reference cell to the first I/O reference line and the second voltage reference cell to the second I/O voltage reference line, and capable of being switched to an off state to isolate at least one of the first voltage reference cell from the first I/O voltage reference line and the second voltage reference cell from the second I/O voltage reference line.

11. The Non-Volatile Resistive memory of claim 1, further comprising:

a third I/O having a third voltage reference cell, coupled by a third voltage reference cell selectable link to a third I/O voltage reference line, and a third sense amplifier coupled to the third I/O voltage reference line; and

another voltage reference line coupling link between the third I/O voltage reference line and at least one of the first I/O voltage reference line and the second I/O voltage reference line,

wherein the third voltage reference cell has a third voltage cell reference voltage output is configured to generate at the third reference cell voltage output a third reference voltage approximately midpoint between the given high read voltage and the given low read voltage.

12. The Non-Volatile Resistive memory of claim 11, wherein said voltage reference line coupling link is a first switchable device and said another voltage reference line coupling link is a second switchable device, said first switchable device being capable of being in an on conducting state concurrent with the second switchable device being in an on conducting state to form the first I/O voltage reference line, the second I/O reference line and the third I/O voltage reference line into a first common voltage node coupled to the first sensing amplifier, the second sensing amplifier and the third sensing amplifier.

13. The Non-Volatile Resistive memory of claim 12, wherein said first switchable device is capable of being in an off non-conducting state concurrent with the second switchable device being in an on conducting state to destroy the first common voltage reference node and form the second I/O voltage reference line and the third I/O line voltage reference line into a second common voltage reference node coupled to the second sensing amplifier and the third amplifier and isolated from the first I/O voltage reference line and the first sensing amplifier.

14. The Non-Volatile Resistive memory of claim 11, wherein said voltage reference line coupling link is a first fusible link and said another voltage reference line coupling link is a second fusible link, to form the first I/O voltage reference line, the second I/O voltage reference line and the third I/O voltage reference line into a first common voltage node.

15. The Non-Volatile Resistive memory of claim 14, wherein the first fusible link is capable of being in a blown state concurrent with the second fusible link being in a conducting state, to destroy the first common voltage node and form the second I/O voltage reference line and the third voltage reference I/O line into a second common voltage reference node coupled to the second sensing amplifier and the third sensing amplifier and isolated from the first I/O voltage reference line and the first sensing amplifier.

16. The Non-Volatile Resistive memory of claim 15, wherein the first voltage reference cell selectable link is a first voltage reference cell fusible link, the second voltage reference cell selectable link is a second voltage reference cell fusible link, and the third voltage reference cell selectable link is a third voltage reference cell fusible link.

17. The Non-Volatile Resistive memory of claim 16, wherein the first voltage reference cell selectable link is capable of being in a blown state concurrent with each of the second voltage reference selectable link and the third voltage reference cell selectable link being in a not blown state, to couple the second voltage reference cell and the third voltage reference cell to the first common voltage reference node concurrent with isolating the first voltage reference cell from the first common voltage reference node.