Semiconductor memory device with oxide semiconductor transistor

• US 8,675,394 B2
• Filed: 07/27/2011
• Issued: 03/18/2014
• Est. Priority Date: 08/04/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsubayashi, Daisuke
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): BUDD, PAUL A
• Application Number:
  US13/191,930
• Publication Number:
  US 20120032161A1
• Time in Patent Office: 965 Days
• Field of Search: 257/4, 257/5, 257/300, 365/149, 365/186, 365/187
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a semiconductor device which can hold stored data even when not powered and which achieves high integration by reduction of the number of wirings. The semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, e.g., an oxide semiconductor material which is a wide bandgap semiconductor. When a semiconductor material which allows a sufficient reduction in the off-state current of a transistor is used, data can be held for a long period. One line serves as the word line for writing and the word line for reading and one line serves as the bit line for writing and the bit line for reading, whereby the number of wirings is reduced. Further, by reducing the number of source lines, the storage capacity per unit area is increased.

Claims

1. A semiconductor device comprising:

n bit lines, n being a natural number;

m memory cells electrically connected to one of the bit lines, m being a natural number; and

m+1 word lines,

wherein each of the memory cells comprises;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and

a capacitor,

wherein the second transistor includes an oxide semiconductor layer,

wherein the one of the bit lines is electrically connected to the first drain electrode and the second drain electrode of a (k−

1)-th memory cell,

wherein a k-th word line is electrically connected to the second gate electrode of a k-th memory cell and is electrically connected to the first source electrode and one electrode of the capacitor of the (k−

1)-th memory cell, k being a natural number of greater than or equal to 2 and less than or equal to m+1, and

wherein the first gate electrode of the (k−

1)-th memory cell, the second source electrode of the (k−

1)-th memory cell, and the other electrode of the capacitor of the (k−

1)-th memory cell are electrically connected to one other.

2. The semiconductor device according to claim 1,

wherein the first transistor comprises:

a first channel formation region provided in a substrate including a semiconductor material;

impurity regions between which the first channel formation region is provided;

a first gate insulating layer over the first channel formation region; and

the first gate electrode provided over the first gate insulating layer so as to overlap with the first channel formation region.

3. The semiconductor device according to claim 1,

wherein the second transistor comprises:

the second source electrode and the second drain electrode that are electrically connected to the oxide semiconductor layer;

the second gate electrode overlapping with the oxide semiconductor layer; and

a second gate insulating layer between the oxide semiconductor layer and the second gate electrode.

4. The semiconductor device according to claim 1, wherein the second transistor has a conductivity type different from a conductivity type of the first transistor.

5. The semiconductor device according to claim 1, wherein the first transistor is a p-channel transistor.

6. The semiconductor device according to claim 2, wherein the substrate including the semiconductor material is a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate or an SOI substrate.

7. The semiconductor device according to claim 2, wherein the semiconductor material is silicon.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes an oxide semiconductor material including In, Ga, and Zn or an oxide semiconductor material including In, Sn, and Zn.

9. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises a crystal.

10. The semiconductor device according to claim 1, wherein the oxide semiconductor is a non-single-crystal oxide including a crystal with c-axis alignment.

11. The semiconductor device according to claim 1, wherein buffer layers are provided between the second source electrode and the oxide semiconductor layer and between the second drain electrode and the oxide semiconductor layer.

12. A semiconductor device comprising:

a first wiring;

a second wiring;

a third wiring;

a first memory cell comprising;

a first transistor comprising;

a first gate;

a first source; and

a first drain;

a second transistor comprising;

a second gate;

a second source; and

a second drain; and

a first capacitor; and

a second memory cell comprising;

a third transistor comprising;

a third gate;

a third source; and

a third drain; and

a fourth transistor comprising;

a fourth gate;

a fourth source; and

a fourth drain;

wherein each of the second transistor and the fourth transistor includes an oxide semiconductor layer,

wherein the first wiring is electrically connected to one of the first source and the first drain, one of the second source and the second drain, one of the third source and the third drain, and one of the fourth source and the fourth drain,

wherein the second wiring is connected to the second gate,

wherein the third wiring is electrically connected to one of electrodes of the first capacitor, and the other of the first source and the first drain,

wherein the third wiring is electrically connected to the fourth gate,

wherein the first gate is electrically connected to the other of the second source and the second drain, and the other of electrodes of the first capacitor, and

wherein the third gate is electrically connected to the other of the fourth source and the fourth drain.

13. The semiconductor device according to claim 12, wherein the second transistor has a conductivity type different from a conductivity type of the first transistor.

14. The semiconductor device according to claim 12, wherein the first transistor and the third transistor are p-channel transistors.

15. The semiconductor device according to claim 12, wherein the first transistor and the third transistor comprise silicon.

16. The semiconductor device according to claim 12, wherein the oxide semiconductor layer includes an oxide semiconductor material including In, Ga, and Zn or an oxide semiconductor material including In, Sn, and Zn.

17. The semiconductor device according to claim 12, wherein the oxide semiconductor comprises a crystal.