Optimal channel design for memory devices for providing a high-speed memory interface
First Claim
Patent Images
1. A system, comprising:
- a plurality of memory devices; and
a channel, comprising;
a transmission line, wherein the transmission line includes thin layers of insulating material between conducting layers and micro-via holes connecting conducting layers through the thin insulating layers; and
an interface circuit, wherein the interface circuit includes a programmable I/O driver operable to be programmed to present any one of a plurality of driver impedances;
wherein the channel is configured to provide electrical communication between a memory controller and a first memory device of the plurality of memory devices, andwherein at least one of a target impedance of the transmission line or a driver impedance of the programmable I/O driver provides impedance matching between the memory controller and the first memory device.
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Abstract
A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.
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Citations
20 Claims
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1. A system, comprising:
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a plurality of memory devices; and a channel, comprising; a transmission line, wherein the transmission line includes thin layers of insulating material between conducting layers and micro-via holes connecting conducting layers through the thin insulating layers; and an interface circuit, wherein the interface circuit includes a programmable I/O driver operable to be programmed to present any one of a plurality of driver impedances; wherein the channel is configured to provide electrical communication between a memory controller and a first memory device of the plurality of memory devices, and wherein at least one of a target impedance of the transmission line or a driver impedance of the programmable I/O driver provides impedance matching between the memory controller and the first memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A sub-system, comprising:
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a first memory device; a circuit board comprising a transmission line, wherein the transmission line includes a thin layer of insulating material between two conducting layers and micro-via holes connecting the conducting layers through the thin layer of insulating material; and an interface circuit configured to present, on a channel between the first memory device and a memory controller, any one of a plurality of driver impedances based on a received command from the memory controller and an effective impedance of the transmission line. - View Dependent Claims (14, 15, 16)
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17. A method comprising:
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providing electrical communication between a memory controller and a memory device through a channel that includes a transmission line that includes thin layers of insulating material between two conducting layers and micro-via holes connecting the conducting layers through the thin insulating layers; receiving a command from the memory controller directed to the memory device; determining a driver impedance based on the received command; and presenting the driver impedance on the channel to match an impedance on the transmission line between the memory controller and the memory device. - View Dependent Claims (18, 19, 20)
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Specification