Optimal channel design for memory devices for providing a high-speed memory interface

• US 8,675,429 B1
• Filed: 08/29/2012
• Issued: 03/18/2014
• Est. Priority Date: 11/16/2007
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, Min, Ferolito, Philip Arnold, Rajan, Suresh Natarajan, Smith, Michael John Sebastian
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US13/597,895
• Time in Patent Office: 566 Days
• Field of Search: 365/72, 365/63, 365/51, 365/198, 365/191
• US Class Current: 365/198
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4234 being a memory bus

Abstract

A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.

Claims

1. A system, comprising:

a plurality of memory devices; and

a channel, comprising;

a transmission line, wherein the transmission line includes thin layers of insulating material between conducting layers and micro-via holes connecting conducting layers through the thin insulating layers; and

an interface circuit, wherein the interface circuit includes a programmable I/O driver operable to be programmed to present any one of a plurality of driver impedances;

wherein the channel is configured to provide electrical communication between a memory controller and a first memory device of the plurality of memory devices, and

wherein at least one of a target impedance of the transmission line or a driver impedance of the programmable I/O driver provides impedance matching between the memory controller and the first memory device.

2. The system of claim 1, wherein the channel includes a respective connection to each of a plurality of dual in-line memory modules (DIMMs), and wherein the first memory device is on a first DIMM of the plurality of DIMMs.

3. The system of claim 2, wherein the channel further comprises a DIMM connector and a resistor stub of the first DIMM.

4. The system of claim 2, wherein the channel is configured to provide an impedance control to adjust signal integrity properties of a read path of the plurality of DIMMs.

5. The system of claim 2, wherein the channel is configured to provide an impedance control to adjust signal integrity properties of a write path of the plurality of DIMMs.

6. The system of claim 2, wherein the interface circuit is on the first DIMM as a flip-chip package.

7. The system of claim 1, wherein the channel includes a connection to a printed circuit board (PCB).

8. The system of claim 7, wherein the printed circuit board includes the transmission line.

9. The system of claim 7, wherein the interface circuit is on the PCB as a flip-chip package.

10. The system of claim 1, wherein the programmable I/O driver provides bi-directional impedance matching between the memory controller and the first memory device.

11. The system of claim 1, wherein the channel includes a read path and a write path.

12. The system of claim 11, wherein the matched impedance of the channel in the read path is substantially equal to the matched impedance of the channel in the write path.

13. A sub-system, comprising:

a first memory device;

a circuit board comprising a transmission line, wherein the transmission line includes a thin layer of insulating material between two conducting layers and micro-via holes connecting the conducting layers through the thin layer of insulating material; and

an interface circuit configured to present, on a channel between the first memory device and a memory controller, any one of a plurality of driver impedances based on a received command from the memory controller and an effective impedance of the transmission line.

14. The sub-system of claim 13, further comprising a channel configured to provide electrical communication between the memory controller and the first memory device, the channel including the transmission line and the interface circuit, wherein at least one of a target impedance of the transmission line or a driver impedance presented by the interface circuit provides impedance matching between the memory controller and the first memory device.

15. The sub-system of claim 13, wherein the channel includes a read path and a write path.

16. The sub-system of claim 15, wherein the matched impedance of the channel in the read path is substantially equal to the matched impedance of the channel in the write path.

17. A method comprising:

providing electrical communication between a memory controller and a memory device through a channel that includes a transmission line that includes thin layers of insulating material between two conducting layers and micro-via holes connecting the conducting layers through the thin insulating layers;

receiving a command from the memory controller directed to the memory device;

determining a driver impedance based on the received command; and

presenting the driver impedance on the channel to match an impedance on the transmission line between the memory controller and the memory device.

18. The method of claim 17, wherein determining a driver impedance based on the received command further comprising determining a first driver impedance based on a read command that is different from a second driver impedance determined based on a write command.

19. The method of claim 18, wherein a matched impedance of the channel in a read path is substantially equal to a matched impedance of the channel in a write path.

20. The method of claim 17, wherein determining a driver impedance further comprising selecting the driver impedance from a plurality of predetermined impedances based on the received command.