Transferring and storing data in multicore and multiprocessor architectures

• US 8,677,081 B1
• Filed: 08/16/2011
• Issued: 03/18/2014
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Original Assignee: Tilera Corporation (NVIDIA Corporation)
• Inventors: Mattina, Matthew, Agarwal, Anant, Wentzlaff, David M.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US13/211,065
• Time in Patent Office: 945 Days
• Field of Search: None
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0824 Distributed directories, e.g. linked lists of caches
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

A processor includes a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is associated with information indicating whether data stored in the cache memory is shared among multiple processor cores.

Claims

1. A processor comprising:

a plurality of cache memories,

an array of interconnected tiles, each tile comprising a processor core, at least one of the tiles comprising a copy engine to perform a memory-to-memory copy operation based on a source begin address, a source end address, a transaction length, and a stride of transaction and each processor core being associated with one of the cache memories;

with the memory-to-memory copy operation copying first segments of data from a source region starting from the begin address, skipping over second segments of data in between the first segments of data, and stopping at the end address, and each of the first segments of data that is copied has a length equal to the transaction length, and each of the second segments of data that is not copied has a length equal to the stride of transaction, and with the source region having the data being copied comprises at least one of a region in a cache memory associated with the tile having the copy engine, a region in a cache memory associated with a tile different from the tile having the copy engine, a region in a cache memory shared by multiple tiles, and a region in a main memory.

2. The processor of claim 1, in which the copy engine performs the memory-to-memory copy operation when the source begin address, source end address, transaction length, and stride of transaction are written into registers without further instruction from the processor core.

3. The processor of claim 1, wherein the copy engine performs the memory-to-memory copy operation when the source begin address, source end address, transaction length, and stride of transaction are written into designated memory regions without further instruction from the processor core.

4. The processor of claim 1, wherein the copy engine issues load and store operations to memory to implement the memory-to-memory copy operation, the load and store operations issued by the copy engine having the same instruction code as load and store operations issued by the processor core.

5. The processor of claim 1, wherein a source region of the memory-to-memory copy operation comprises at least two of a region in a cache memory associated with the tile having the copy engine, a region in a cache memory associated with a tile different from the tile having the copy engine, a region in a cache memory shared by multiple tiles, and a region in a main memory.

6. The processor of claim 1, wherein a destination region of the memory-to-memory copy operation comprises at least one of a region in a cache memory associated with the tile having the copy engine, a region in a cache memory associated with a tile different from the tile having the copy engine, a region in a cache memory shared by multiple tiles, and a region in a main memory.

7. The processor of claim 6, wherein a destination region of the memory-to-memory copy operation comprises at least two of a region in a cache memory associated with the tile having the copy engine, a region in a cache memory associated with a tile different from the tile having the copy engine, a region in a cache memory shared by multiple tiles, and a region in a main memory.

8. The processor of claim 1, wherein the memory-to-memory copy operation comprises a direct memory access operation.

9. The processor of claim 1, wherein every tile comprises a copy engine.

10. A method comprising:

performing a memory-to-memory copy operation when a begin address, an end address, a transaction length, and a stride value are written into predetermined registers without requiring further instructions from a processor core, including

copying first segments of data from a source region starting from the begin address and stopping at the end address, and

skipping over second segments of data in between the first segments of data,

with each of the first segments of data that is copied has a length equal to the transaction length, and each of the second segments of data that is not copied has a length equal to the stride value, and with the source region having the data being copied comprises at least one of a region in a cache memory associated with the tile having the copy engine, a region in a cache memory associated with a tile different from the tile having the copy engine, a region in a cache memory shared by multiple tiles, and a region in a main memory.

11. The method of claim 10, comprising performing a second memory-to-memory copy operation, in which the transaction length associated with the second memory-to-memory copy operation is different from the transaction length associated with the first memory-to-memory copy operation.

12. The method of claim 10, wherein the memory-to-memory copy operation is performed when the source begin address, source end address, transaction length, and stride of transaction are written into registers without further instruction from the processor core.

13. The method of claim 10, wherein the memory-to-memory copy operation is performed when the source begin address, source end address, transaction length, and stride of transaction are written into designated memory regions without further instruction from the processor core.

14. The method of claim 10, wherein a copy engine issues load and store operations to memory to implement the memory-to-memory copy operation, the load and store operations issued by the copy engine having the same instruction code as load and store operations issued by the processor core.

15. The method of claim 10, wherein a source region of the memory-to-memory copy operation comprises at least two of a region in a cache memory associated with the tile having the copy engine, a region in a cache memory associated with a tile different from the tile having the copy engine, a region in a cache memory shared by multiple tiles, and a region in a main memory.

16. The method of claim 10, wherein a destination region of the memory-to-memory copy operation comprises at least one of a region in a cache memory associated with the tile having the copy engine, a region in a cache memory associated with a tile different from the tile having the copy engine, a region in a cache memory shared by multiple tiles, and a region in a main memory.

17. The method of claim 16, wherein a destination region of the memory-to-memory copy operation comprises at least two of a region in a cache memory associated with the tile having the copy engine, a region in a cache memory associated with a tile different from the tile having the copy engine, a region in a cache memory shared by multiple tiles, and a region in a main memory.

18. The method of claim 10, wherein the memory-to-memory copy operation comprises a direct memory access operation.

19. The method of claim 10, wherein every tile comprises a copy engine.