Electronic device comprising error correction coding device and electronic device comprising error correction decoding device
First Claim
1. An electronic device comprising an error correction coding device, which comprises a parity code generator for computing a remainder polynomial by dividing a user data polynomial by a generator polynomial and generating a parity code from the remainder polynomial,wherein the parity code generator comprises:
- an input part for dividing and inputting either a first bit string comprising coefficients of the generator polynomial or the first bit string and a second bit string comprising of the user data polynomial;
a first operation part for computing the remainder polynomial by splitting a division operation into multiple division operations based on either a division width of the user data polynomial or a division width of the user data polynomial and the generator polynomial; and
a first output part for outputting a third bit string comprising coefficients of the remainder polynomial, which is a result of the division by the first operation part.
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Accused Products
Abstract
An electronic device comprises an error correction coding device. The error correction coding device comprises a parity code generator. This generator is a circuit for computing a remainder polynomial by dividing a user data polynomial by a generator polynomial and generating a parity code from this remainder polynomial. This generator computes the remainder polynomial by dividing and inputting either a bit string comprising coefficients of the generator polynomial, or a bit string comprising coefficients of the generator polynomial and a bit string comprising coefficients of the generator polynomial, and dividing a minimal unit multiple times based on either a division width of the user polynomial or a division width of the user polynomial and the generator polynomial, and outputs a bit string comprising the coefficient of this remainder polynomial.
19 Citations
13 Claims
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1. An electronic device comprising an error correction coding device, which comprises a parity code generator for computing a remainder polynomial by dividing a user data polynomial by a generator polynomial and generating a parity code from the remainder polynomial,
wherein the parity code generator comprises: -
an input part for dividing and inputting either a first bit string comprising coefficients of the generator polynomial or the first bit string and a second bit string comprising of the user data polynomial; a first operation part for computing the remainder polynomial by splitting a division operation into multiple division operations based on either a division width of the user data polynomial or a division width of the user data polynomial and the generator polynomial; and a first output part for outputting a third bit string comprising coefficients of the remainder polynomial, which is a result of the division by the first operation part. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An error correction coding device, which comprises a parity code generator for computing a remainder polynomial by dividing a user data polynomial by a generator polynomial, and generating a parity code from the remainder polynomial,
wherein the parity code generator comprises: -
an input part for dividing and inputting either a first bit string comprising coefficients of the generator polynomial or the first bit string and a second bit string comprising coefficients of the user data polynomial; and an operation part for computing the remainder polynomial by splitting a division operation into multiple division operations based on either a division width of the user data polynomial or a division width of the user data polynomial and the generator polynomial.
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Specification