Method and apparatus for adapting a bit interleaver to LDPC codes and modulations under AWGN channel conditions using binary erasure surrogate channels

• US 8,677,219 B2
• Filed: 10/02/2009
• Issued: 03/18/2014
• Est. Priority Date: 10/03/2008
• Status: Expired due to Fees

• Current Assignee: Thomson Licensing (Vantiva SA)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Lei, Jing, Gao, Wen
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Ahmed, Enam
• Application Number:
  US12/998,270
• Publication Number:
  US 20110182345A1
• Time in Patent Office: 1,628 Days
• Field of Search: 714/774
• US Class Current: 714/774
• CPC Class Codes: H03M 13/11 using multiple parity bits
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/251 with block coding
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/2757 Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
• CPC Class Codes: H03M 13/356 Unequal error protection [UEP]
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 27/36 Modulator circuits; Transmitter circuits

Abstract

The present invention relates to code-dependent bit interleavers for parallel non-uniform channels. Since the channel dependence of a given code ensemble is dominated by the mutual information between the channel input and output, the present invention proposes to simplify the analysis about the decoding behavior by using a set of surrogate binary erasure channels. The approximation of the actual channel by the surrogate BEC is established on the equivalence of bitwise capacities, which represent the mutual information between the uniformly-distributed binary input and the likelihood ratios of the effective parallel AWGN channels. Moreover, the transition of the erasure probabilities is modeled by a linear difference equation around the decoding threshold SNR, from which we can derive a necessary condition on the convergence of decoding iterations and achieve a useful guideline for the configuration of the bit interleaver.

Claims

1. A method for configuring a bit interleaver to LDPC codes and modulations comprising:

calculating a bitwise capacity of non-uniform parallel AWGN channels;

approximating said AWGN channels with a set of Q surrogate binary erasure channels with an erasure probability;

determining whether a decoding threshold signal-to-noise ratio results in a lowest decoding threshold signal-to-noise ratio for a bit interleaver configuration using erasure probability density distributions; and

configuring the bit interleaver based on the bit interleaver configuration corresponding to the determined lowest decoding threshold signal-to-noise ratio, wherein said determining further comprises;

reducing the SNR by a predetermined step size when the erasure probability converges to zero;

determining the erasure probability for the reduced SNR;

determining whether the erasure probability of the reduced SNR converges to zero; and

identifying the SNR prior to said reducing as the decoding threshold SNR for the bit interleaver configuration when the erasure probability does not converge to zero.

2. The method of claim 1, wherein said determining further comprises:

increasing the SNR by a predetermined step size when the erasure probability does not converge to zero;

determining the erasure probability for the increased SNR;

determining whether the erasure probabiligy for the increased SNR converges to zero; and

identifying the increased SNR as the decoding threshold SNR for the bit interleaver configuration when the erasure probabilty converges to zero.

3. The method according to claim 2, further comprising the steps of:

storing each bit interleaver configuration and corresponding determined lowest decoding threshold SNR;

changing the bit interleaver configuration (Λ

);

performing said step of determining to determine the decoding threshold SNR for the changed bit interleaver configuration;

selecting a bit interleaver configuration having the lowest decoding threshold SNR; and

configuring the bit interleaver with the selected configuration.

4. The method according to claim 1, wherein said determining further comprises determining an average erasure probability density distribution modeled from a predetermined linear difference equation from the decoding threshold SNR.

5. The method of claim 4, wherein said determining of the average erasure probability further comprises:

identifying node/edge perspective degree distributions of the LDPC code;

convex combining of the erasure probability of each subchannel.

6. The method according to claim 4, wherein the density distribution modeling is derived from the following:

7. The method according to claim 2, further comprising minimizing the decoding threshold SNR by constraining optimization of a degree profile of the bit interleaver.

8. An apparatus for configuring a bit interleaver to LDPC codes and modulations comprising:

a processor configured to calculate a bitwise capacity of non-uniform parallel AWGN channels, to approximate the AWGN channels with a set of surrogate binary erasure channels, and to determine a decoding threshold SNR for each of one or more bit interleaver configurations using erasure probability density distributions, wherein said processor determines an erasure probability for each determined SNR;

a memory for storing the one or more determined decoding threshold SNR and corresponding bit interleaver configuration; and

a bit interleaver being configured by said processor based on the bit interleaver configuration corresponding to a selected lowest decoding threshold SNR from the stored one or more determined decoding threshold SNR, wherein the processor further determines an average erasure probability density distribution modeled from a predetermined linear difference equation from the determined one or more decoding threshold SNR.

9. The apparatus according to claim 8, wherein the processor determines the average erasure probability by identifying node/edge perspective degree distributions of the LDPC code, and convex combining of the erasure probability of each subchannel.

10. The apparatus according to claim 9, wherein the density distribution modeling is derived from the following:

11. A method for configuring a receiver bit interleaver to LDPC codes and modulations comprising:

calculating a bitwise capacity of non-uniform parallel AWGN channels;

approximating said AWGN channels with a set of Q surrogate binary erasure channels with an erasure probability;

determining whether a decoding threshold signal-to-noise ratio results in a lowest decoding threshold signal-to-noise ratio for a bit interleaver configuration using erasure probability density distributions; and

configuring the receiver bit interleaver based on the bit interleaver configuration corresponding to the determined lowest decoding threshold signal-to-noise ratio, wherein said determining further comprises;

reducing the SNR by a predetermined step size when the erasure probability converges to zero;

determining the erasure probability for the reduced SNR;

determining whether the erasure probability of the reduced SNR converges to zero; and

identifying the SNR prior to said reducing as the decoding threshold SNR for the bit interleaver configuration when the erasure probability does not converge to zero.

12. The method of claim 11, wherein said determining further comprises:

increasing the SNR by a predetermined step size when the erasure probability does not converge to zero;

determining the erasure probability for the increased SNR;

determining whether the erasure probabiligy for the increased SNR converges to zero; and

identifying the increased SNR as the decoding threshold SNR for the bit interleaver configuration when the erasure probabilty converges to zero.

13. The method according to claim 12, further comprising the steps of:

storing each bit interleaver configuration and corresponding determined lowest decoding threshold SNR;

changing the bit interleaver configuration (Λ

);

performing said step of determining to determine the decoding threshold SNR for the changed bit interleaver configuration;

selecting a bit interleaver configuration having the lowest decoding threshold SNR; and

configuring the bit interleaver with the selected configuration.

14. The method according to claim 11, wherein said determining further comprises determining an average erasure probability density distribution modeled from a predetermined linear difference equation from the decoding threshold SNR.

15. The method of claim 14, wherein said determining of the average erasure probability further comprises:

identifying node/edge perspective degree distributions of the LDPC code;

convex combining of the erasure probability of each subchannel.

16. The method according to claim 14, wherein the density distribution modeling is derived from the following:

17. The method according to claim 12, further comprising minimizing the decoding threshold SNR by constraining optimization of a degree profile of the bit interleaver.

18. An apparatus for configuring a receiver bit interleaver to LDPC codes and modulations comprising:

a processor configured to calculate a bitwise capacity of non-uniform parallel AWGN channels, to approximate the AWGN channels with a set of surrogate binary erasure channels, and to determine a decoding threshold SNR for each of one or more bit interleaver configurations using erasure probability density distributions, wherein said processor determines an erasure probability for each determined SNR;

a memory for storing the one or more determined decoding threshold SNR and corresponding bit interleaver configuration; and

a receiver bit interleaver being configured by said processor based on the bit interleaver configuration corresponding to a selected lowest decoding threshold SNR from the stored one or more determined decoding threshold SNR, wherein the processor further determines an average erasure probability density distribution modeled from a predetermined linear difference equation from the determined one or more decoding threshold SNR.

19. The apparatus according to claim 18, wherein the processor determines the average erasure probability by identifying node/edge perspective degree distributions of the LDPC code, and convex combining of the erasure probability of each subchannel.

20. The apparatus according to claim 18, wherein the density distribution modeling is derived from the following:

21. A method for configuring a bit interleaver to LDPC codes and modulations comprising:

calculating a bitwise capacity of non-uniform parallel AWGN channels;

approximating said AWGN channels with a set of Q surrogate binary erasure channels with an erasure probability;

determining whether a decoding threshold signal-to-noise ratio results in a lowest decoding threshold signal-to-noise ratio for a bit interleaver configuration using erasure probability density distributions; and

configuring the bit interleaver based on the bit interleaver configuration corresponding to the determined lowest decoding threshold signal-to-noise ratio, wherein said calculated bitwise capacity further comprises calculating the bitwise capacity based on mutual information between a binary input and an effective output of the parallel AWGN channels, said approximating being based on an equivalence of the calculated bitwise capacity.

22. An apparatus for configuring a bit interleaver to LDPC codes and modulations comprising:

a processor configured to calculate a bitwise capacity of non-uniform parallel AWGN channels, to approximate the AWGN channels with a set of surrogate binary erasure channels, and to determine a decoding threshold SNR for each of one or more bit interleaver configurations using erasure probability density distributions, wherein said processor determines an erasure probability for each determined SNR;

a memory for storing the one or more determined decoding threshold SNR and corresponding bit interleaver configuration; and

a bit interleaver being configured by said processor based on the bit interleaver configuration corresponding to a selected lowest decoding threshold SNR from the stored one or more determined decoding threshold SNR, wherein the processor calculates the bitwise capacity based on mutual information between a binary input and an effective output of the parallel AWGN channels.

23. An apparatus for configuring a bit interleaver to LDPC codes and modulations comprising:

a processor configured to calculate a bitwise capacity of non-uniform parallel AWGN channels, to approximate the AWGN channels with a set of surrogate binary erasure channels, and to determine a decoding threshold SNR for each of one or more bit interleaver configurations using erasure probability density distributions, wherein said processor determines an erasure probability for each determined SNR;

a memory for storing the one or more determined decoding threshold SNR and corresponding bit interleaver configuration; and

a bit interleaver being configured by said processor based on the bit interleaver configuration corresponding to a selected lowest decoding threshold SNR from the stored one or more determined decoding threshold SNR, wherein said bit interleaver is configured to bit interleave the code based on conditions for decoding convergence of decoding iterations derived from each determined erasure probability corresponding to each respective threshold SNR.

24. A method for configuring a receiver bit interleaver to LDPC codes and modulations comprising:

calculating a bitwise capacity of non-uniform parallel AWGN channels;

approximating said AWGN channels with a set of Q surrogate binary erasure channels with an erasure probability;

determining whether a decoding threshold signal-to-noise ratio results in a lowest decoding threshold signal-to-noise ratio for a bit interleaver configuration using erasure probability density distributions; and

configuring the receiver bit interleaver based on the bit interleaver configuration corresponding to the determined lowest decoding threshold signal-to-noise ratio, wherein said calculated bitwise capacity further comprises calculating the bitwise capacity based on mutual information between a binary input and an effective output of the parallel AWGN channels, said approximating being based on an equivalence of the calculated bitwise capacity.

25. An apparatus for configuring a receiver bit interleaver to LDPC codes and modulations comprising:

a processor configured to calculate a bitwise capacity of non-uniform parallel AWGN channels, to approximate the AWGN channels with a set of surrogate binary erasure channels, and to determine a decoding threshold SNR for each of one or more bit interleaver configurations using erasure probability density distributions, wherein said processor determines an erasure probability for each determined SNR;

a memory for storing the one or more determined decoding threshold SNR and corresponding bit interleaver configuration; and

a receiver bit interleaver being configured by said processor based on the bit interleaver configuration corresponding to a selected lowest decoding threshold SNR from the stored one or more determined decoding threshold SNR, wherein the processor calculates the bitwise capacity based on mutual information between a binary input and an effective output of the parallel AWGN channels.