Method and system for model-based design and layout of an integrated circuit

• US 8,677,301 B2
• Filed: 06/27/2012
• Issued: 03/18/2014
• Est. Priority Date: 06/05/2008
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Lai, Ya-Chieh, Gennari, Frank, Moskewicz, Matthew, Doddi, Srinivas, Lei, Junjiang, Fang, Weiping, Lay, Kuanghao
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US13/535,225
• Publication Number:
  US 20120272200A1
• Time in Patent Office: 629 Days
• Field of Search: 716/55, 716/126
• US Class Current: 716/126
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

Claims

1. A system for routing an electronic design, comprising:

a non-transitory computer readable medium comprising a copy of an electronic design that is to undergo routing;

a model related to a manufacturing process to manufacture the electronic design, wherein the model comprises a set of patterns; and

a placement or routing tool to route the electronic design to generate a hotspot-free layout, without using a separate electronic circuit verification tool, to verify at least a portion of the electronic design, the router having an integrated module for performing pattern matching using the set of patterns.

2. The system of claim 1 in which the set of patterns comprises patterns that have been previously analyzed to find hotspots using the customer'"'"'s expected manufacturing facility and process parameters to predict the as-manufactured result based upon the representative layout.

3. The system of claim 1 in which the set of patterns comprises good patterns, bad patterns, or both good and bad patterns.

4. The system of claim 1 in which the module for performing pattern matching is used to search for hotspots during routing.

5. The system of claim 1 in which the routing implemented by the router is free from the identified hotspots.

6. The system of claim 1 in which a design rule check is performed by the router, wherein a design rule check library includes a rule based upon hotspot analysis.

7. The system of claim 6 in which a rule based upon a hotspot analysis includes a pattern that can be used by a pattern matcher.

8. A computer implemented method for routing an electronic design, comprising:

at least one processor that is to perform a process, the process comprising;

identifying a copy of a layout for the electronic design that is to undergo routing;

identifying or determining a model related to a manufacturing process to manufacture the electronic design, wherein the model comprises a set of patterns;

performing pattern matching with a placement or routing tool using the set of patterns; and

routing the electronic design to generate a hotspot-free layout by using the placement or routing tool, rather than using a separate electronic circuit verification tool, to verify at least a portion of the electronic design based at least in part upon a result of the pattern matching.

9. The computer implemented method of claim 8, in which the set of patterns comprises patterns that have been previously analyzed to find hotspots using the customer'"'"'s expected manufacturing facility and process parameters to predict the as-manufactured result based upon the representative layout.

10. The computer implemented method of claim 8, the process further comprising:

searching for one or more hotspots using the placement or routing tool during the action of routing the layout.

11. The computer implemented method of claim 8, in which the layout implemented by the placement or routing tool is free from identified hotspots.

12. The computer implemented method of claim 8, the process further comprising:

performing design rule check by using the placement or routing tool based at least in part upon a design rule check library, in which the design rule check library includes a rule based at least in part upon hotspot analysis.

13. The computer implemented method of claim 12, in which a rule for the design rule check includes a pattern that is to be used by a pattern matcher.

14. The computer implemented method of claim 8, the act of routing the electronic design comprising:

canonicalizing multiple patterns into a single canonical pattern.

15. A computer program product comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor, causes the at least one processor to execute a method for routing an electronic design, the method comprising:

using at least one processor to perform a process, the process comprising;

identifying a copy of the electronic design that is to undergo routing;

identifying or determining a model related to a manufacturing process to manufacture the electronic design, wherein the model comprises a set of patterns;

performing pattern matching with a placement or routing tool using the set of patterns; and

routing the electronic design to generate a hotspot-free layout by using the placement or routing tool, rather than using a separate electronic circuit verification tool, to verify at least a portion of the electronic design based at least in part upon a result of the pattern matching.

16. The computer program product of claim 15, in which the set of patterns comprises patterns that have been previously analyzed to find hotspots using the customer'"'"'s expected manufacturing facility and process parameters to predict the as-manufactured result based upon the representative layout.

17. The computer program product of claim 15, the process further comprising:

searching for one or more hotspots using the placement or routing tool during the action of routing the layout.

18. The computer program product of claim 15, in which the layout implemented by the placement or routing tool is free from identified hotspots.

19. The computer program product of claim 15, the process further comprising:

performing design rule check by using the placement or routing tool based at least in part upon a design rule check library, in which the design rule check library includes a rule based at least in part upon hotspot analysis.

20. The computer program product of claim 19, in which a rule for the design rule check includes a pattern that is to be used by a pattern matcher.