Generation of compiler description from architecture description
First Claim
1. A computer implemented method of generating a compiler description from an architecture description, comprising:
- extracting information from an architecture description describing an architecture, the extracted information including instruction latencies and data hazard information of the architecture resulting from temporal input/output behavior of instructions;
transmitting instructions to present a graphical user interface;
receiving, via an interaction with the graphical user interface, definitions for a plurality of abstract elements of a compiler that have no direct representative in the architecture description;
extracting a mapping of compiler rules to instructions included in the architecture description; and
automatically generating a compiler description of the compiler for the architecture based on the extracted information, the received definitions for the plurality of abstract elements, and the extracted mapping.
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Abstract
A computer implemented method of generating a compiler description from an architecture description. Information is automatically extracted from an architecture description that is usable in a description of an architecture described by the architecture description. The extracted information is imported into a program comprising a graphical user interface that accepts user provided additional information that is usable in the compiler description. User provided additional information is accessed that is usable in the compiler description. A compiler description is automatically generated for the architecture described by the architecture description, based on the automatically extracted information and the accessed user provided additional information.
79 Citations
11 Claims
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1. A computer implemented method of generating a compiler description from an architecture description, comprising:
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extracting information from an architecture description describing an architecture, the extracted information including instruction latencies and data hazard information of the architecture resulting from temporal input/output behavior of instructions; transmitting instructions to present a graphical user interface; receiving, via an interaction with the graphical user interface, definitions for a plurality of abstract elements of a compiler that have no direct representative in the architecture description; extracting a mapping of compiler rules to instructions included in the architecture description; and automatically generating a compiler description of the compiler for the architecture based on the extracted information, the received definitions for the plurality of abstract elements, and the extracted mapping. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A computer system comprising a processor and a computer readable medium coupled to the processor via a bus, wherein said computer readable medium comprises instructions that when executed by said processor implement a method of generating a compiler description from an architecture description, comprising:
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extracting information from an architecture description describing an architecture the extracted information including instruction latencies and data hazard information of the architecture resulting from temporal input/output behavior of instructions; transmitting instructions to present a graphical user interface; receiving, via an interaction with the graphical user interface, definitions for a plurality of abstract elements of a compiler that have no direct representative in the architecture description; extracting a mapping of compiler rules to instructions included in the architecture description; and automatically generating a compiler description of the compiler for the architecture based on the extracted information, the received definitions for the plurality of abstract elements, and the extracted mapping. - View Dependent Claims (9, 10, 11)
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Specification