Microelectronic device and MEMS package structure and fabricating method thereof

• US 8,679,886 B2
• Filed: 12/26/2012
• Issued: 03/25/2014
• Est. Priority Date: 08/11/2009
• Status: Active Grant

• Current Assignee: PixArt Imaging Incorporated
• Original Assignee: PixArt Imaging Incorporated
• Inventors: Hsu, Hsin-Hui, Lee, Sheng-Ta, Wang, Chuan-Wei
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): Quinto, Kevin
• Application Number:
  US13/727,072
• Publication Number:
  US 20130119441A1
• Time in Patent Office: 454 Days
• Field of Search: None
• US Class Current: 438/50
• CPC Class Codes: B81B 3/0018 Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
• CPC Class Codes: B81C 1/00015 for manufacturing microsystems
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures

Abstract

A microelectronic device including a substrate, at least a semi-conductor element, an anti metal ion layer, a non-doping oxide layer and a MEMS structure is provided. The substrate has a CMOS circuit region and a MEMS region. The semi-conductor element is configured within the CMOS circuit region of the substrate. The anti metal ion layer is disposed within the CMOS circuit region of the substrate and covers the semi-conductor element. The non-doping oxide layer is disposed on the substrate within the MEMS region. The MEMS structure is partially suspended above the non-doping oxide layer. The present invention also provides a MEMS package structure and a fabricating method thereof.

Claims

1. A MEMS package structure, comprising:

a substrate;

a MEMS structure partially suspended above the substrate;

a metallic layer with a plurality of first openings disposed above the MEMS structure;

a mask layer with a plurality of second openings disposed above the metallic layer, wherein the second openings and the first openings are staggered with each other; and

a packaging layer disposed on the mask layer and filling into the second openings so as to connect to the metallic layer.

2. The MEMS package as claimed in claim 1, wherein materials of the mask layer and the packaging layer comprises metallic material or amorphous silicon.

3. The MEMS package as claimed in claim 2, wherein the materials of the mask layer and the packaging layer comprises aluminum.

4. A method for fabricating a MEMS package, comprising:

providing a substrate;

forming a plurality of metallic layers, a plurality of contact plugs and a plurality of oxide layers so as to compose a MEMS structure, wherein one of the metallic layers disposed above the MEMS structure has a plurality of first openings;

forming a mask layer with a plurality of second openings on the top one of the metallic layers, the second openings and the first openings being staggered with each other;

removing predetermined portions of the oxide layers by employing the first openings and the second openings as etching channels, thereby making the MEMS structure partially suspended above the substrate; and

forming a packaging layer on the mask layer, the packaging layer filling into the second openings, thereby sealing the MEMS structure between the metallic layers and the substrate.

5. The method for fabricating a MEMS package as claimed in claim 4, wherein a removing method of the predetermined portions of the oxide layers comprises hydrofluoric acid vapor etching.