Electronic device comprising a conductive structure and an insulating layer within a trench and a process of forming the same

• US 8,679,919 B2
• Filed: 12/15/2011
• Issued: 03/25/2014
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Venkatraman, Prasad, Grivna, Gordon M., Loechelt, Gary H.
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US13/327,361
• Publication Number:
  US 20130153987A1
• Time in Patent Office: 831 Days
• Field of Search: 257/118, 257/244, 257328-333, 257/466, 257/513, 257/594, 257/E29.262, 257/E21.41
• US Class Current: 438/268
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.

Claims

1. A process of forming an electronic device comprising:

forming a semiconductor layer over a substrate, wherein the semiconductor layer has a primary surface and a thickness;

patterning the semiconductor layer to define a first trench extending through at least approximately 50% of the thickness of the semiconductor layer;

forming a first insulating layer within the first trench;

forming a vertically-oriented doped region within the semiconductor layer and extending from near the primary surface towards the substrate, wherein the vertically-oriented doped region is formed after patterning the semiconductor layer to define the first trench;

forming a first conductive structure within the first trench, wherein the first insulating layer is disposed between the semiconductor layer and the first conductive structure; and

forming a gate electrode, wherein substantially all of the gate electrode overlies the primary surface of the semiconductor layer.

2. The process of claim 1, wherein patterning the semiconductor layer is performed such that, other than rounding at a bottom of the first trench, the first trench has a substantially uniform width.

3. The process of claim 1, wherein forming the first conductive structure comprises:

filling a first portion of the first trench with a first conductive fill material;

removing a portion, but not all, of the first insulating layer within the first trench after filling the first portion of the trench with the first conductive fill material; and

filling a second portion of the trench with a second conductive fill material after removing a portion, but not all, of the first insulating layer.

4. The process of claim 1, wherein forming the vertically-oriented doped region and forming the first conductive structure comprise:

filling the first trench with a first conductive fill material;

removing a portion, but not all, of the first conductive fill material;

forming the vertically-oriented doped region after removing the portion of the first conductive fill material; and

filling a second portion of the first trench with a second conductive fill material after forming the vertically-oriented doped region.

5. The process of claim 1, wherein forming the gate electrode comprises:

forming a gate electrode layer; and

anisotropically etching the gate electrode layer to form a gate member, wherein anisotropically etching removes substantially an entire thickness of the gate electrode layer from over a portion of the first conductive structure.

6. The process of claim 5, further comprising forming a patterned resist layer over the gate electrode layer, wherein anisotropically etching is performed while the resist layer overlies the gate electrode layer.

7. The process of claim 1, further comprising:

patterning the semiconductor layer to define a second trench that extends through at least approximately 50% of the thickness of semiconductor layer, wherein the second trench is spaced-apart from the first trench;

forming a second insulating layer within the second trench;

forming a second conductive structure within the second trench after forming the second insulating layer; and

forming a source region outside of and adjacent to the second trench, wherein the source region is spaced apart from the vertically-oriented doped region by a channel region.

8. The process of claim 7, wherein:

forming the first insulating layer comprises forming a first insulating film within the first and second trenches, and forming a second insulating film within the first and second trenches after forming the first insulating film; and

removing a portion, but not all, of the first insulating layer comprises selectively etching the second insulating film in preference to the first insulating film within the first trench, and not etching a significant amount of the second insulating film within the second trench.

9. The process of claim 7, wherein forming the vertically-oriented doped region, forming the first conductive structure, and forming the second conductive structure comprise:

filling the first and second trenches with a first conductive fill material;

removing a portion, but not all, of the first conductive fill material from within the first trench, and not removing a significant portion of the first conductive fill material from the second trench;

forming the vertically-oriented doped region immediately adjacent to a sidewall of the first trench after removing the portion of the first conductive fill material, wherein no vertically-oriented doped region is formed immediately adjacent to a sidewall of the second trench; and

filling a second portion of the first trench with a second conductive fill material after forming the vertically-oriented doped region.

10. The process of claim 1, wherein patterning the semiconductor layer is performed such that the bottom of the first trench is substantially U-shaped.

11. The process of claim 1, wherein forming the first insulating layer is performed such that the first insulating layer is significantly thicker along a bottom of the first trench compared to any other portion of the first insulating layer along a sidewall of the first trench.

12. The process of claim 1, wherein forming the first insulating layer is performed such that the first insulating layer has a thickness of between approximately 50 nm and approximately 300 nm.

13. The process of claim 1, wherein forming the first insulating layer is performed such that the first insulating layer has a thickness of between approximately 110 nm and approximately 200 nm.

14. The process of claim 1, wherein forming the vertically-oriented doped region is performed such that the vertically-oriented doped region extends of a depth that is at least approximately 20% of the thickness of the semiconductor layer.

15. The process of claim 7, wherein:

forming the first insulating layer is performed such that the first insulating layer is significantly thicker along a bottom of the first trench compared to any other portion of the first insulating layer along a sidewall of the first trench;

forming the second insulating layer is performed such that the second insulating layer is significantly thicker along a bottom of the second trench compared to any other portion of the second insulating layer along a sidewall of the second trench;

or

any combination thereof.

16. The process of claim 7, wherein:

forming the first insulating layer is performed such that the first insulating layer has a thickness of between approximately 50 nm and approximately 300 nm;

forming the second insulating layer is performed such that the second insulating layer has a thickness of between approximately 50 nm and approximately 300 nm;

or

any combination thereof.

17. A process of forming an electronic device comprising:

forming a semiconductor layer over a substrate, wherein the semiconductor layer has a primary surface and a thickness;

patterning the semiconductor layer to define a first trench extending through at least approximately 50% of the thickness of the semiconductor layer, wherein, other than rounding at a bottom of the first trench, the first trench has a substantially uniform width;

forming a first insulating layer within the first trench;

forming a vertically-oriented doped region within the semiconductor layer and extending from near the primary surface towards the substrate, wherein the vertically-oriented doped region is formed after patterning the semiconductor layer to define the first trench; and

forming a first conductive structure within the first trench, wherein the first insulating layer is disposed between the semiconductor layer and the first conductive structure.

18. A process of forming an electronic device comprising:

forming a semiconductor layer over a substrate, wherein the semiconductor layer has a primary surface and a thickness;

patterning the semiconductor layer to define a first trench extending through at least approximately 50% of the thickness of the semiconductor layer;

forming a first insulating layer within the first trench;

forming a vertically-oriented doped region within the semiconductor layer and extending from near the primary surface towards the substrate, wherein the vertically-oriented doped region is formed after patterning the semiconductor layer to define the first trench; and

forming a first conductive structure within the first trench, wherein the first insulating layer is disposed between the semiconductor layer and the first conductive structure, and wherein forming the vertically-oriented doped region and forming the first conductive structure comprise;

filling the first trench with a first conductive fill material;

removing a portion, but not all, of the first conductive fill material;

forming the vertically-oriented doped region after removing the portion of the first conductive fill material; and

filling a second portion of the first trench with a second conductive fill material after forming the vertically-oriented doped region.