Method of depositing a diffusion barrier for copper interconnect applications

• US 8,679,972 B1
• Filed: 05/29/2013
• Issued: 03/25/2014
• Est. Priority Date: 03/13/2001
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Danek, Michal, Klawuhn, Erich, Rozbicki, Robert
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): Stevenson, Andre
• Application Number:
  US13/904,464
• Time in Patent Office: 300 Days
• Field of Search: None
• US Class Current: 438/662
• CPC Class Codes: H01J 37/32082 Radio frequency generated discharge H01J37/32357, H01J37/32366, H01J37/32394 and H01J37/32403 take precedence
• CPC Class Codes: H01L 21/02043 Cleaning before device manufacture, i.e. Begin-Of-Line process
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76862 Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

Claims

1. A method for depositing a metal-containing material on a substrate, the method comprising:

(a) receiving a wafer substrate comprising at least one via comprising a bottom part and at least one trench, wherein the substrate comprises an exposed metal at the bottom part of the at least one via, and wherein at least one via is unlanded;

(b) depositing a first portion of the metal-containing material at least over the bottom part of the at least one via using a metal from a deposition source;

(c) etching away the first portion of the metal-containing material at the bottom part of the at least one via with energetic inert gas ions without fully etching through to partially remove the first portion of the metal-containing material such that a part of the first portion of the metal-containing material remains at the bottom part of the at least one via and a portion of the first portion of the metal-containing material is removed from the bottom part of the at least one via, such that the resistance of subsequently formed interconnects is reduced relative to that of interconnects formed using the first portion of the metal-containing material prior to etching, while simultaneously depositing a second portion of the metal-containing material in the at least one trench and/or field on the wafer substrate.

2. The method of claim 1, wherein (c) is performed with an etch rate to deposition rate (E/D) ratio of greater than 1 at the bottom of the at least one via and an (E/D) of less than 1 on a via sidewall.

3. The method of claim 1, wherein (c) is performed with an E/D ratio of greater than 1 at the bottom of the at least one via and an (E/D) of less than 1 at the bottom of the trench.

4. The method of claim 1, wherein (c) is performed with an E/D ratio of greater than 1 at the bottom of the at least one via and an (E/D) of less than 1 on a field region of the substrate.

5. The method of claim 1, wherein in (a) the unlanded via comprises an exposed dielectric at the bottom of the unlanded via.

6. The method of claim 1, wherein the metal-containing material deposited in (c) comprises Ta or TaN.

7. The method of claim 1, wherein (b) comprises depositing a first portion of the metal-containing material using atomic layer deposition (ALD).

8. The method of claim 1, wherein (b) comprises depositing a first portion of the metal-containing material using physical vapor deposition (PVD).

9. The method of claim 8, wherein (b) and (c) are performed in the same PVD process chamber and wherein (b) comprises applying a first power to a deposition source and (c) comprises applying a lower power to the deposition source.

10. The method of claim 1, further comprising pre-cleaning the bottom portion of the at least one via prior to (b).

11. The method of claim 1, wherein the exposed metal at the bottom of the at least one via comprises copper.

12. The method of claim 1, wherein the first portion of the metal-containing material deposited in (b) forms a conformal coating.