Semiconductor device

• US 8,680,520 B2
• Filed: 11/18/2010
• Issued: 03/25/2014
• Est. Priority Date: 11/20/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Carpenter, Robert
• Application Number:
  US12/949,631
• Publication Number:
  US 20110121285A1
• Time in Patent Office: 1,223 Days
• Field of Search: 257/43
• US Class Current: 257/43
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor including a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided over a substrate including a semiconductor material, and the second transistor includes an oxide semiconductor layer.

Claims

1. A semiconductor device comprising:

a source line;

a bit line;

a signal line; and

a word line,

wherein a plurality of memory cells are connected in parallel between the source line and the bit line,

wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,

wherein the first transistor is provided in a substrate containing a semiconductor material,

wherein the second transistor comprises an oxide semiconductor layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,

wherein the source line and one of the first source electrode and the first drain electrode are electrically connected to each other,

wherein the bit line and the other of the first source electrode and the first drain electrode are electrically connected to each other, and

wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.

2. The semiconductor device according to claim 1, wherein the signal line and the second gate electrode are electrically connected to each other.

3. The semiconductor device according to claim 1, wherein the second transistor comprises the second gate electrode over the substrate containing the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode which are electrically connected to the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

5. The semiconductor device according to claim 1, wherein the semiconductor material is silicon.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor material.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

8. The semiconductor device according to claim 1, wherein hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

9. The semiconductor device according to claim 1, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

10. A semiconductor device comprising:

a source line;

a bit line;

a signal line;

a word line;

a first selection line;

a second selection line;

a third transistor which is electrically connected to the first selection line in a third gate electrode; and

a fourth transistor which is electrically connected to the second selection line in a fourth gate electrode,

wherein a plurality of memory cells are connected in parallel between the source line and the bit line,

wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,

wherein the first transistor is provided in a substrate containing a semiconductor material,

wherein the second transistor comprises an oxide semiconductor layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,

wherein the source line and one of the first source electrode and the first drain electrode are electrically connected to each other through the fourth transistor,

wherein the bit line and the other of the first source electrode and the first drain electrode are electrically connected to each other through the third transistor, and

wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.

11. The semiconductor device according to claim 10,

wherein the signal line and the second gate electrode are electrically connected to each other.

12. The semiconductor device according to claim 10, wherein the second transistor comprises the second gate electrode over the substrate containing the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode which are electrically connected to the oxide semiconductor layer.

13. The semiconductor device according to claim 10, wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

14. The semiconductor device according to claim 10, wherein the semiconductor material is silicon.

15. The semiconductor device according to claim 10, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor material.

16. The semiconductor device according to claim 10, wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

17. The semiconductor device according to claim 10, wherein hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

18. The semiconductor device according to claim 10, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

19. A semiconductor device comprising:

a source line;

a bit line;

a signal line; and

a word line,

wherein a plurality of memory cells are connected in parallel between the source line and the bit line,

wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,

wherein the first transistor is provided in a substrate containing a semiconductor material,

wherein the second transistor comprises an oxide semiconductor layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,

wherein the source line and one of the first source electrode and the first drain electrode are electrically connected to each other,

wherein the bit line and the other of the first source electrode and the first drain electrode are electrically connected to each other,

wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another, and

wherein the first transistor comprises a channel formation region provided in the substrate containing the semiconductor material, impurity regions provided so as to interpose the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode which are electrically connected to the impurity regions.

20. The semiconductor device according to claim 19,

wherein the signal line and the second gate electrode are electrically connected to each other.

21. The semiconductor device according to claim 19, wherein the second transistor comprises the second gate electrode over the substrate containing the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode which are electrically connected to the oxide semiconductor layer.

22. The semiconductor device according to claim 19, wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

23. The semiconductor device according to claim 19, wherein the semiconductor material is silicon.

24. The semiconductor device according to claim 19, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor material.

25. The semiconductor device according to claim 19, wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

26. The semiconductor device according to claim 19, wherein hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

27. The semiconductor device according to claim 19, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

28. A semiconductor device comprising:

a source line;

a bit line;

a signal line;

a word line;

a first selection line;

a second selection line;

a third transistor which is electrically connected to the first selection line in a third gate electrode; and

a fourth transistor which is electrically connected to the second selection line in a fourth gate electrode,

wherein a plurality of memory cells are connected in parallel between the source line and the bit line,

wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,

wherein the first transistor is provided in a substrate containing a semiconductor material,

wherein the second transistor comprises an oxide semiconductor layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,

wherein the source line and one of the first source electrode and the first drain electrode are electrically connected to each other through the fourth transistor,

wherein the bit line and the other of the first source electrode and the first drain electrode are electrically connected to each other through the third transistor,

wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another, and

wherein the first transistor comprises a channel formation region provided in the substrate containing the semiconductor material, impurity regions provided so as to interpose the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode which are electrically connected to the impurity regions.

29. The semiconductor device according to claim 28,

wherein the signal line and the second gate electrode are electrically connected to each other.

30. The semiconductor device according to claim 28, wherein the second transistor comprises the second gate electrode over the substrate containing the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode which are electrically connected to the oxide semiconductor layer.

31. The semiconductor device according to claim 28, wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

32. The semiconductor device according to claim 28, wherein the semiconductor material is silicon.

33. The semiconductor device according to claim 28, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor material.

34. The semiconductor device according to claim 28, wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

35. The semiconductor device according to claim 28, wherein hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

36. The semiconductor device according to claim 28, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.