Semiconductor device
First Claim
Patent Images
1. A semiconductor device comprising:
- a source line;
a bit line;
a signal line; and
a word line,wherein a plurality of memory cells are connected in parallel between the source line and the bit line,wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,wherein the first transistor is provided in a substrate containing a semiconductor material,wherein the second transistor comprises an oxide semiconductor layer,wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,wherein the source line and one of the first source electrode and the first drain electrode are electrically connected to each other,wherein the bit line and the other of the first source electrode and the first drain electrode are electrically connected to each other, andwherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.
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Abstract
It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor including a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided over a substrate including a semiconductor material, and the second transistor includes an oxide semiconductor layer.
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Citations
36 Claims
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1. A semiconductor device comprising:
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a source line; a bit line; a signal line; and a word line, wherein a plurality of memory cells are connected in parallel between the source line and the bit line, wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor, wherein the first transistor is provided in a substrate containing a semiconductor material, wherein the second transistor comprises an oxide semiconductor layer, wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another, wherein the source line and one of the first source electrode and the first drain electrode are electrically connected to each other, wherein the bit line and the other of the first source electrode and the first drain electrode are electrically connected to each other, and wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device comprising:
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a source line; a bit line; a signal line; a word line; a first selection line; a second selection line; a third transistor which is electrically connected to the first selection line in a third gate electrode; and a fourth transistor which is electrically connected to the second selection line in a fourth gate electrode, wherein a plurality of memory cells are connected in parallel between the source line and the bit line, wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor, wherein the first transistor is provided in a substrate containing a semiconductor material, wherein the second transistor comprises an oxide semiconductor layer, wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another, wherein the source line and one of the first source electrode and the first drain electrode are electrically connected to each other through the fourth transistor, wherein the bit line and the other of the first source electrode and the first drain electrode are electrically connected to each other through the third transistor, and wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor device comprising:
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a source line; a bit line; a signal line; and a word line, wherein a plurality of memory cells are connected in parallel between the source line and the bit line, wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor, wherein the first transistor is provided in a substrate containing a semiconductor material, wherein the second transistor comprises an oxide semiconductor layer, wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another, wherein the source line and one of the first source electrode and the first drain electrode are electrically connected to each other, wherein the bit line and the other of the first source electrode and the first drain electrode are electrically connected to each other, wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another, and wherein the first transistor comprises a channel formation region provided in the substrate containing the semiconductor material, impurity regions provided so as to interpose the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode which are electrically connected to the impurity regions. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. A semiconductor device comprising:
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a source line; a bit line; a signal line; a word line; a first selection line; a second selection line; a third transistor which is electrically connected to the first selection line in a third gate electrode; and a fourth transistor which is electrically connected to the second selection line in a fourth gate electrode, wherein a plurality of memory cells are connected in parallel between the source line and the bit line, wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor, wherein the first transistor is provided in a substrate containing a semiconductor material, wherein the second transistor comprises an oxide semiconductor layer, wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another, wherein the source line and one of the first source electrode and the first drain electrode are electrically connected to each other through the fourth transistor, wherein the bit line and the other of the first source electrode and the first drain electrode are electrically connected to each other through the third transistor, wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another, and wherein the first transistor comprises a channel formation region provided in the substrate containing the semiconductor material, impurity regions provided so as to interpose the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode which are electrically connected to the impurity regions. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36)
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Specification