Semiconductor device
First Claim
1. A semiconductor device comprising a transistor, the transistor comprising:
- a gate electrode layer;
a gate insulating layer adjacent to the gate electrode layer; and
an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween,wherein a channel length formed in the oxide semiconductor layer is 0.2 μ
m to 3.0 μ
m,wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm,wherein a thickness of the gate insulating layer is 20 nm to 50 nm,wherein the oxide semiconductor layer includes a region in which a concentration of hydrogen is 5×
1019/cm3 or less, andwherein an off current per micrometer in a channel width is 100 aA/μ
m or less when a drain voltage of 1 V to 10 V is applied.
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Abstract
An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.
108 Citations
20 Claims
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1. A semiconductor device comprising a transistor, the transistor comprising:
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a gate electrode layer; a gate insulating layer adjacent to the gate electrode layer; and an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween, wherein a channel length formed in the oxide semiconductor layer is 0.2 μ
m to 3.0 μ
m,wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm, wherein a thickness of the gate insulating layer is 20 nm to 50 nm, wherein the oxide semiconductor layer includes a region in which a concentration of hydrogen is 5×
1019/cm3 or less, andwherein an off current per micrometer in a channel width is 100 aA/μ
m or less when a drain voltage of 1 V to 10 V is applied. - View Dependent Claims (2, 3, 4)
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5. A semiconductor device comprising a transistor, the transistor comprising:
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a gate electrode layer; a gate insulating layer adjacent to the gate electrode layer; and an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween, wherein a channel length formed in the oxide semiconductor layer is 0.2 μ
m to 3.0 μ
m,wherein a thickness of the oxide semiconductor layer is 15 nm to 100 nm, wherein a thickness of the gate insulating layer is 10 nm to 20 nm, wherein the oxide semiconductor layer includes a region in which a concentration of hydrogen is 5×
1019/cm3 or less, andwherein an off current per micrometer in a channel width is 100 aA/μ
m or less when a drain voltage of 1 V to 10 V is applied. - View Dependent Claims (6, 7, 8)
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9. A semiconductor device comprising a transistor, the transistor comprising:
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a gate electrode layer; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping the gate electrode layer with the gate insulating layer therebetween; source and drain electrode layers over the oxide semiconductor layer, the source and drain electrode layers overlapping parts of the oxide semiconductor layer; and an oxide insulating layer over the source and drain electrode layers, the oxide insulating layer being in contact with the oxide semiconductor layer, wherein a channel length formed in the oxide semiconductor layer is 0.2 μ
m to 3.0 μ
m,wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm, wherein a thickness of the gate insulating layer is 20 nm to 50 nm, wherein the oxide semiconductor layer includes a region in which a concentration of hydrogen is 5×
1019/cm3 or less, andwherein an off current per micrometer in a channel width is 100 aA/μ
m or less when a drain voltage of 1 V to 10 V is applied. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A semiconductor device comprising a transistor, the transistor comprising:
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a gate electrode layer; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping the gate electrode layer with the gate insulating layer therebetween; source and drain electrode layers over the oxide semiconductor layer, the source and drain electrode layers overlapping parts of the oxide semiconductor layer; and an oxide insulating layer over the source and drain electrode layers, the oxide insulating layer being in contact with the oxide semiconductor layer, wherein a channel length formed in the oxide semiconductor layer is 0.2 μ
m to 3.0 μ
m,wherein a thickness of the oxide semiconductor layer is 15 nm to 100 nm, wherein a thickness of the gate insulating layer is 10 nm to 20 nm, wherein the oxide semiconductor layer includes a region in which a concentration of hydrogen is 5×
1019/cm3 or less, andwherein an off current per micrometer in a channel width is 100 aA/μ
m or less when a drain voltage of 1 V to 10 V is applied. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification