CMOS device and method of forming the same

• US 8,680,576 B2
• Filed: 05/16/2012
• Issued: 03/25/2014
• Est. Priority Date: 05/16/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Ju, Shi Ning, Lo, Cary Chia-Chiung, Chang, Huicheng, Su, Chun Chung
• Primary Examiner(s): Blum, David S
• Application Number:
  US13/473,149
• Publication Number:
  US 20130307021A1
• Time in Patent Office: 678 Days
• Field of Search: 257/15, 257/18, 257/19, 257/28, 257/190, 257/308, 257/E39.011, 257/E33.009, 257/E33.01, 257/E31.035, 257/E31.036, 257/E29.073, 257/E21.427, 257/E29.193, 257/E29.298, 257/E21.125, 257/618, 257/E21.09, 257/E21.339, 257/E29.255, 438/190
• US Class Current: 257/190
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.

Claims

1. A semiconductor device, comprising:

a substrate including a first region and a second region;

a first buffer layer formed over the substrate and between first and second isolation features in the first region, the first and second isolation features being distinct from the substrate, the first buffer layer having a first width;

a second buffer layer formed over the substrate and between third and fourth isolation features in the second region, the third and fourth isolation features being distinct from the substrate, the second buffer layer having a second width different from the first width of the first buffer layer;

a first fin structure formed over the first buffer layer and between the first and second isolation features in the first region; and

a second fin structure formed over the second buffer layer and between the third and fourth isolation features in the second region.

2. The semiconductor device of claim 1 further comprising:

first dislocations features formed within the first buffer layer operable to relax the first buffer layer; and

second dislocations features formed within the second buffer layer operable to relax the second buffer layer.

3. The semiconductor device of claim 1 wherein the first buffer layer includes a first lattice constant,

wherein the second buffer layer includes a second lattice constant,

wherein the first and second lattice constants are substantially the same,

wherein the first fin structure includes a third lattice constant less than the first and second lattice constants, and

wherein the second fin structure includes a fourth lattice constant greater than the first and second lattice constants.

4. The semiconductor device of claim 1 wherein the first buffer layer includes first facets having a vertical dimension of less than about 20% of a width of the first fin structure and a longitudinal dimension of less than about 25% of the width of the first fin structure, and

wherein the second buffer layer includes second facets having a vertical dimension of less than about 50% of a width of the second fin structure and a longitudinal dimension ranging from about 45% to about 25% of the width of the second fin structure.

5. The semiconductor device of claim 1 wherein the first buffer layer is substantially facet free, and

wherein the second buffer layer includes facets having a vertical dimension less than about 5 nm and a longitudinal dimension less than about 4.5 nm.

6. The semiconductor device of claim 4 wherein the first region is a NMOS region, and

wherein the second region is a PMOS region.

7. The semiconductor device of claim 4 wherein the first region is a PMOS region, and

wherein the second region is a NMOS region.

8. A semiconductor device, comprising:

a substrate including a first region and a second region;

isolation features distinct from the substrate and formed within trenches of the substrate in the first and second regions;

a first buffer layer including first facets formed over the substrate and between the isolation features in the first region;

a second buffer layer including second facets different from the first facets and formed over the substrate and between the isolation features in the second region;

a first semiconductor material formed over the first facets of the first buffer layer and between the isolation features in the first region; and

a second semiconductor material formed over the second facets of the second buffer layer and between the isolation features in the second region, the second semiconductor material being different from the first semiconductor material,

wherein the buffer layer in the first region includes a total height different from a total height of the buffer layer in the second region.

9. The semiconductor device of claim 8 further comprising:

dislocations features formed within the first buffer layer operable to relax the buffer layer in the first and second regions.

10. The semiconductor device of claim 9 wherein the first semiconductor material is in tensile stress, and

wherein the second semiconductor material is in compressive stress.

11. The semiconductor device of claim 9 wherein the substrate includes a first lattice constant,

wherein the buffer layer includes a second lattice constant greater than the first lattice constant,

wherein the first semiconductor material includes a third lattice constant less than the second lattice constant, and

wherein the second semiconductor material includes a fourth lattice constant greater than the second lattice constant.

12. The semiconductor device of claim 9 wherein the substrate includes silicon (Si),

wherein the first and second buffer layers include silicon germanium (SiGe),

wherein the first semiconductor material includes silicon (Si), and

wherein the second semiconductor material includes germanium (Ge).

13. The semiconductor device of claim 11 wherein the total height of the first buffer layer in the first region is less than the total height of the second buffer layer in the second region.

14. The semiconductor device of claim 11 wherein the total height of the first buffer layer in the first region is greater than the total height of the second buffer layer in the second region.

15. A semiconductor device, comprising:

a substrate including a first region and a second region;

isolation features formed within trenches of the substrate in the first and second regions;

a buffer layer formed over the substrate and between the isolation features in the first and second regions;

a first semiconductor material formed over the buffer layer and between the isolation features in the first region; and

a second semiconductor material formed over the buffer layer and between the isolation features in the second region, the second semiconductor material being different from the first semiconductor material,

wherein the buffer layer in the first region includes a total height different from a total height of the buffer layer in the second region.

wherein the buffer layer in the first region includes facets having facets a vertical dimension less than about 2 nm and a longitudinal dimension less than about 2.5 nm, and

wherein the buffer layer in the second region includes facets having a vertical dimension ranging from about 5 nm to about 2 nm and a longitudinal dimension ranging from about 4.5 nm to about 2.5 nm.

16. A semiconductor device, comprising:

a substrate including a first region and a second region;

two shallow trench isolation (STI) features distinct from the substrate and formed in the first region;

two STI features distinct from the substrate and formed in the second region;

a first buffer layer formed between the two STI features in the first region;

a second buffer layer formed between the two STI features in the second region;

a first semiconductor material formed over the buffer layer and between the two STI features in the first region, wherein the first semiconductor material is in physical contact with the two STI features in the first region;

a second semiconductor material formed over the buffer layer and between the two STI features in the second region,

wherein the first buffer layer includes a top most surface facing away from a top most surface of the substrate in the first region that is below a top most surface of the two STI features in the first region,

wherein the second buffer layer includes a top most surface facing away from a top most surface of the substrate in the second region that is below a top most surface of the two STI features in the second region.

17. The semiconductor device of claim 16 wherein the first semiconductor material includes a top most surface that is above the top most surface of the two STI features of in the first region, and

wherein the second semiconductor material includes a top most surface that is above the top most surface of the two STI features of in the second region.

18. The semiconductor device of claim 16 wherein the top most surface of the first buffer layer is at a height different from the top most surface of the second buffer layer.

19. The semiconductor device of claim 16 wherein a width of the first buffer layer is different from a width of the second buffer layer.