Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

• US 8,680,601 B2
• Filed: 09/26/2007
• Issued: 03/25/2014
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Jenne, Fredrick B., Ramkumar, Krishnaswamy, Levy, Sagy
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): YUSHINA, GALINA G
• Application Number:
  US11/904,475
• Publication Number:
  US 20080290399A1
• Time in Patent Office: 2,372 Days
• Field of Search: 257324-326, 257/E29.309, 257/E21.423, 257/315, 257/225, 257/300, 257/314, 257/E27.084, 257/E27.085, 257/E27.098, 257/E21.209, 257/E21.21, 257/E21.434, 257/E21.646, 257/E21.662, 257/E21.679, 257/E29.331, 257/239, 257/261, 438/216, 438/431, 438/308
• US Class Current: 257/314
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Claims

1. A nonvolatile charge trap memory device, comprising:

a substrate having a channel region, a source region and a drain region; and

a gate stack disposed above the substrate over the channel region and between the source region and the drain region, wherein the gate stack comprises a multi-layer charge-trapping region having a first layer and a second layer, the first layer between the channel region and the second layer, wherein the second layer is separate from the first layer and wherein the first layer comprises deuterium and is trap free, and the second layer is a deuterium-free charge-trapping layer.

2. The nonvolatile charge trap memory device of claim 1, wherein the multi-layer charge-trapping region further comprises a third layer, wherein the second layer is between the first layer and the third layer, and wherein the third layer comprises deuterium.

3. The nonvolatile charge trap memory device of claim 2, wherein a total thickness of the multi-layer charge-trapping region is in a range of 5-10 nanometers.

4. The nonvolatile charge trap memory device of claim 3, wherein a ratio of a thickness of the first layer and a thickness of the third layer is substantially 1:

1.

5. The nonvolatile charge trap memory device of claim 2 wherein the gate stack further comprises a tunnel dielectric layer disposed above the substrate over the channel region, and wherein the multi-layer charge-trapping region is disposed above the tunnel dielectric layer.

6. The nonvolatile charge trap memory device of claim 5 further comprising a top dielectric layer disposed on the third layer of the multi-layer charge-trapping region.

7. The nonvolatile charge trap memory device of claim 6 wherein the top dielectric layer comprises deuterium.

8. The nonvolatile charge trap memory device of claim 1 wherein the first layer comprises a deuterated derivative of a dielectric material and the second layer comprises a non-deuterated derivative of the same dielectric material.

9. The nonvolatile charge trap memory device of claim 8 wherein the dielectric material comprises a silicon-nitride.

10. The nonvolatile charge trap memory device of claim 8 wherein the dielectric material comprises a silicon oxy-nitride.

11. The nonvolatile charge trap memory device of claim 10 wherein silicon oxy-nitride comprises a silicon-rich silicon oxy-nitride.

12. The nonvolatile charge trap memory device of claim 1 wherein the gate stack further comprises a tunnel dielectric layer disposed above the substrate over the channel region, and wherein the multi-layer charge-trapping region is disposed above the tunnel dielectric layer.

13. The nonvolatile charge trap memory device of claim 12 further comprising a top dielectric layer disposed on the second layer of the multi-layer charge-trapping region.

14. The nonvolatile charge trap memory device of claim 13 wherein the top dielectric layer comprises deuterium.