Nonvolatile semiconductor memory device and method of manufacturing the same
First Claim
1. A nonvolatile semiconductor memory device, comprising:
- a first region configured to function as a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and
a second region provided in a periphery of the first region,the first region comprising;
a first semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate;
a charge storage layer formed on a side surface of the columnar portion; and
a plurality of first conductive layers formed on the charge storage layer, and configured to function as a control electrode of the memory cells,andthe second region comprising a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers,the plurality of first conductive layers configuring a stepped portion at an end vicinity of the first region, the stepped portion being formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another, andthe plurality of second conductive layers being formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate.
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Accused Products
Abstract
A first region comprises: a semiconductor layer including a columnar portion, a charge storage layer, and a plurality of first conductive layers. The second region comprises: a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers. The plurality of first conductive layers configure a stepped portion at an end vicinity of the first region. The stepped portion is formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The plurality of second conductive layers is formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate.
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Citations
9 Claims
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1. A nonvolatile semiconductor memory device, comprising:
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a first region configured to function as a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and a second region provided in a periphery of the first region, the first region comprising; a first semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate; a charge storage layer formed on a side surface of the columnar portion; and a plurality of first conductive layers formed on the charge storage layer, and configured to function as a control electrode of the memory cells, and the second region comprising a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers, the plurality of first conductive layers configuring a stepped portion at an end vicinity of the first region, the stepped portion being formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another, and the plurality of second conductive layers being formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 9)
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8. A nonvolatile semiconductor memory device, comprising:
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a first region configured to function as a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series, the first region comprising; a semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate; a charge storage layer formed on a side surface of the columnar portion; a plurality of conductive layers formed on the charge storage layer, and configured to function as a control electrode of the memory cells; a stepped portion having the plurality of conductive layers formed in a stepped shape such that positions of ends of the plurality of conductive layers differ from one another; and a wall portion provided adjacently to the stepped portion and formed by the plurality of conductive layers such that positions of ends of the plurality of conductive layers are aligned in substantially the perpendicular direction to the substrate; wherein the stepped portion comprises; a first stepped portion formed so as to decrease in height in a stepwise manner proceeding from a first position to a second position in the first direction, and to increase in height in a stepwise manner proceeding from the second position to a third position in the first direction; and a second stepped portion formed so as to decrease in height in a stepwise manner proceeding from the third position to a fourth position in the first direction, and to increase in height in a stepwise manner proceeding from the fourth position to a fifth position in the first direction, the first stepped portion and the second stepped portion each having an asymmetrical shape.
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Specification