Termination design for high voltage device

• US 8,680,613 B2
• Filed: 07/30/2012
• Issued: 03/25/2014
• Est. Priority Date: 07/30/2012
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Guan, Lingpeng, Bhalla, Anup, Yilmaz, Hamza
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US13/561,300
• Publication Number:
  US 20140027840A1
• Time in Patent Office: 603 Days
• Field of Search: 257/333, 257330-331, 257/335, 257/341, 257/E21.41, 438270-271
• US Class Current: 257/333
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer of the first conductivity type disposed on a top surface of the semiconductor substrate, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped;

an active cell array including a body region of a second conductivity type that is opposite of the first conductivity type, a source region of the first conductivity type and a gate disposed near the top surface of the surface shielded region and a drain disposed at a bottom surface of the semiconductor substrate, a plurality of trenches formed in the surface shielded region, wherein the trenches are lined with a trench insulation material and filled with an electrically conductive trench filling material configured to be in electrical contact with a source electrode on top of the surface shielded region and in electrical contact with the source region, and a plurality of buried doped regions of the second conductivity type, wherein each buried doped region is positioned below one of the plurality of trenches, and wherein the buried doped regions extend to a depth substantially the same as the bottom surface of the surface shielded region;

a termination region surrounding the active cell array, the termination comprising two or more zones and an electrical disconnect configured to prevent an electrical short between the body layer and an edge of the semiconductor device;

wherein, the termination region is formed in the epitaxial layer, wherein the termination region includes a plurality termination structures, each of the termination structures comprising, a trench shield electrode and a buried doped-region of the second conductivity type such that a cumulative depth of the trench and buried region is substantially the same as a depth of the surface shielded region;

wherein each termination structure in a first zone closest to the active region includes an electrical connection between its trench shield electrode and a portion of the body layer closer to the active cell array; and

wherein each termination structure in a second zone includes an electrical connection between its trench shield electrode and a portion of the body layer further away from the active cell array, and a spacing between each termination structure in the second zone increases with increasing distance away from the active cell array.

2. The device of claim 1, wherein the buried doped regions are linked to the body layer by a link region of the same conductivity type as the body and buried doped regions, wherein the link region is disposed along sidewalls of the trenches.

3. The device of claim 2, wherein the electrical disconnect is a third termination zone comprising a floating electrode, configured to create a disconnect between the body region and the link region, wherein the floating electrode is formed between two additional termination structures, each of the additional termination structures comprising, a trench shield electrode and a buried doped-region of the second conductivity type, wherein a cumulative depth of the trench and buried region is substantially the same as a depth of the surface shielded region.

4. The device of claim 1 wherein the electrical disconnect is formed by a portion of the surface shielded region that is positioned between the body layer and the buried doped-region.

5. The device of claim 1 wherein each of the active cell structures in the active cell array are field balance metal oxide field effect transistors (FBMs).

6. The device of claim 1 wherein the epitaxial layer and structures formed therein are configured such that the surface shielded region is sufficiently doped to support approximately one-third of the semiconductor device'"'"'s breakdown voltage and the voltage blocking region is sufficiently doped to support approximately two-thirds of the semiconductor device'"'"'s breakdown voltage.

7. The device of claim 1 wherein a doping concentration of the surface shielded region is 5-100 times greater than a doping concentration of the voltage blocking region.