Customized shield plate for a field effect transistor

• US 8,680,615 B2
• Filed: 12/13/2011
• Issued: 03/25/2014
• Est. Priority Date: 12/13/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mitra, Agni, Burdeaux, David C.
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): Garcia, Joannie A
• Application Number:
  US13/324,910
• Publication Number:
  US 20130146973A1
• Time in Patent Office: 833 Days
• Field of Search: 257/335, 257/340
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.

Claims

1. A transistor, comprising:

a semiconductor substrate including a surface layer extending from an upper surface of the semiconductor substrate to a surface depth;

a gate dielectric overlying a channel region of the surface layer;

a gate electrode overlying the gate dielectric, the gate electrode including a first sidewall and a second sidewall;

a source region comprising a portion of the surface region extending between the channel region and a source contact region;

a drift region comprising a portion of the surface region extending between the channel region and a drain region;

a shield interlevel dielectric (ILD) overlying at least a portion of an upper surface of the gate electrode, the second sidewall, and a portion of the drift region;

a shield plate comprising an electrically conductive layer overlying at least a portion of the shield ILD, the shield plate defining a shield plate edge overlying the drift region, wherein the shield plate edge comprises a customized shield plate edge wherein a displacement between the customized shield plate edge and the second sidewall varies along a length of the second sidewall.

2. The transistor of claim 1, wherein the shield plate comprises a first shield, the shield plate edge comprises a first shield plate edge, and the shield ILD comprises a first shield ILD and wherein the transistor includes:

a second shield ILD including a portion overlying at least a portion of the upper surface of the gate electrode, the second sidewall, and a portion of the drift region; and

a second shield plate comprising an electrically conductive layer overlying at least a portion of the second shield ILD, the second shield plate defining a second shield plate edge overlying a second shield ILD.

3. The transistor of claim 2, wherein the second shield plate edge defines a second customized shield plate edge overlying the drift region, wherein a displacement between the second shield plate edge and the second sidewall varies along a length of the second sidewall.

4. The transistor of claim 2, wherein the second shield plate defines a parallel shield plate edge wherein a displacement between the second shield plate edge and the second sidewall remains substantially constant along a length of the second sidewall.

5. The transistor of claim 4, wherein a displacement between the second shield plate edge and the second sidewall is greater than the displacement between the first shield plate edge and the second sidewall.

6. The transistor of claim 4, wherein a displacement between the first shield plate edge and the second sidewall is greater than a displacement between the second shield plate edge and the second sidewall.

7. The transistor of claim 2, wherein the second shield plate overlies the first shield plate.

8. The transistor of claim 7, wherein the displacement between the first shield plate edge and the second sidewall exceeds a displacement between the second shield plate edge and the second sidewall along a first portion of the first shield plate edge and wherein the displacement between the first shield plate edge and the second sidewall is less than a displacement between the second shield plate edge and the second sidewall along a second portion of the first shield plate edge.

9. The transistor of claim 2, wherein a thickness of the first shield plate ILD differs from a thickness of the second shield plate ILD.

10. The transistor of claim 2, wherein a thickness of the first shield plate differs from a thickness of the second shield plate.

11. The transistor of claim 2, wherein the first shield plate is comprised of a first shield plate material and the second shield plate comprises a second shield plate material, wherein the first shield plate material differs from a second shield plate material.

12. The transistor of claim 1, wherein the shield plate is comprised of a silicide.

13. The transistor of claim 1, wherein shield plate edge comprises a plurality of line segments.

14. The transistor of claim 1, wherein the shield plate edge is configured to achieve a predetermined electrical characteristic of the shield plate.

15. A semiconductor device, comprising:

a semiconductor layer including a surface layer extending from an upper surface of the semiconductor layer to a surface depth;

a gate dielectric overlying the surface layer;

a gate electrode including a first sidewall and a second sidewall defining lateral boundaries of a channel region of the surface layer;

a shield interlevel dielectric (ILD) including a portion overlying at least a portion of an upper surface of the gate electrode, the first sidewall, and a drift region of the surface region, the drift region being adjacent the channel region;

a customized shield plate comprising a conductive layer overlying at least a portion of the shield ILD, the shield plate defining a customized shield plate edge overlying the drift region, wherein a portion of the customized shield plate edge is non parallel to the second sidewall.

16. The semiconductor device of claim 15, wherein the customized shield plate FET comprises a lateral diffused metal oxide semiconductor transistor.

17. The semiconductor device of claim 15, wherein a second shield plate overlying at least a portion of the customized shield plate.