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Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices

  • US 8,680,629 B2
  • Filed: 06/03/2009
  • Issued: 03/25/2014
  • Est. Priority Date: 06/03/2009
  • Status: Active Grant
First Claim
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1. A material stack formed on a semiconductor substrate of a semiconductor structure having first and second regions, comprising:

  • an interface preparation layer formed on the semiconductor substrate, in both the first and second regions;

    a high-k dielectric layer having a high dielectric constant greater than approximately 3.9, the high-k dielectric layer present over both the first and the second regions, wherein the high-k dielectric layer is formed directly on the interface preparation layer in the second region;

    a germanium (Ge) material layer formed only in the first region, wherein the Ge material layer is formed directly on the interface preparation layer in the first region and the high-k dielectric layer is formed directly on the Ge material layer in the first region;

    a metal nitride layer formed only in the second region, wherein the metal nitride layer is formed directly on the high-k dielectric layer in the second region; and

    a conductive electrode layer formed over both the first and the second regions.

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