Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices

• US 8,680,629 B2
• Filed: 06/03/2009
• Issued: 03/25/2014
• Est. Priority Date: 06/03/2009
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Jagannathan, Hemanth, Ando, Takashi, Narayanan, Vijay
• Primary Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US12/477,536
• Publication Number:
  US 20100308412A1
• Time in Patent Office: 1,756 Days
• Field of Search: None
• US Class Current: 257/407
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.

Claims

1. A material stack formed on a semiconductor substrate of a semiconductor structure having first and second regions, comprising:

an interface preparation layer formed on the semiconductor substrate, in both the first and second regions;

a high-k dielectric layer having a high dielectric constant greater than approximately 3.9, the high-k dielectric layer present over both the first and the second regions, wherein the high-k dielectric layer is formed directly on the interface preparation layer in the second region;

a germanium (Ge) material layer formed only in the first region, wherein the Ge material layer is formed directly on the interface preparation layer in the first region and the high-k dielectric layer is formed directly on the Ge material layer in the first region;

a metal nitride layer formed only in the second region, wherein the metal nitride layer is formed directly on the high-k dielectric layer in the second region; and

a conductive electrode layer formed over both the first and the second regions.

2. The material stack of claim 1, further comprising a conductive layer disposed on top of the conductive electrode layer, the conductive layer present over both the first and the second regions.

3. The material stack of claim 2, wherein the conductive layer comprises one of a Si-containing conductive layer or a metallic conductive layer.

4. The material stack of claim 1, wherein the interface preparation layer comprises a chemical oxide, a thermal oxide or an oxynitride layer.

5. The material stack of claim 1, wherein the Ge material layer comprises Ge or a Ge compound.

6. The material stack of claim 1, wherein a thickness of the Ge material layer is less than or equal to approximately 2 nanometers (nm).

7. A semiconductor structure, comprising:

a patterned material stack disposed on a surface of a semiconductor substrate, the patterned material stack comprising;

an interface preparation layer formed on the semiconductor substrate;

a high-k dielectric layer having a high dielectric constant greater than approximately 3.9, the high-k dielectric layer formed on the interface preparation layer; and

a germanium (Ge)-containing metal electrode formed on the high-k dielectric layer, wherein the Ge-containing metal electrode comprises MGe where M denotes a conductive metal electrode material selected from the group consisting of titanium germanium nitride (TiGeN) and tantalum germanium carbon (TaGeC).

8. A method of forming a semiconductor structure having a first semiconductor device including a first patterned material stack and a second semiconductor device including a second patterned material stack, the method comprising:

providing a semiconductor substrate, the first patterned material stack formed over a first region of the substrate and the second patterned material stack formed over a second region of the substrate;

forming an interface preparation layer in the first and second patterned material stacks;

forming a metal nitride layer on the interface preparation layer of only the first patterned material stack;

forming a high-k dielectric layer, having a high dielectric constant greater than approximately 3.9, on the metal nitride layer of the first patterned material stack, and on the interface preparation layer of the second patterned material stack;

forming a Ge material layer on the high-k dielectric of both the first and second patterned material stacks; and

forming a conductive electrode layer above the Ge material layer of both the first and second patterned material stacks.

9. A method of forming a semiconductor structure having a first semiconductor device including a first patterned material stack and a second semiconductor device including a second patterned material stack, the method comprising:

providing a semiconductor substrate, the first patterned material stack formed over a first region of the substrate and the second patterned material stack formed over a second region of the substrate;

forming a high-k dielectric having a high dielectric constant greater than approximately 3.9;

forming a metal nitride layer in the first patterned material stack interfacing with the high-k dielectric;

forming a Ge material layer only in the second patterned material stack interfacing with the high-k dielectric;

forming a conductive electrode layer above the high-k dielectric, the Ge material layer, or the metal nitride layer; and

forming the metal nitride layer in the second patterned material stack interfacing with the high-k-dielectric.