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Wafer level edge stacking

  • US 8,680,662 B2
  • Filed: 06/15/2009
  • Issued: 03/25/2014
  • Est. Priority Date: 06/16/2008
  • Status: Active Grant
First Claim
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1. A microelectronic assembly, comprising:

  • a first microelectronic device and a second microelectronic device, each of the microelectronic devices including a die structure including at least one semiconductor die, andeach of the microelectronic devices having a first surface, a second surface opposite the first surface, at least one edge surface extending at an angle other than a right angle away from the first and second surfaces, and at least one first electrically conductive element extending along the first surface and onto the at least one of the edge surface and contacting at least one second electrically conductive element, the at least one second electrically conductive element extending along the second surface so as to be opposite the first electrically conductive element along the first surface in a direction of thickness of the assembly, at least one of the first or second conductive elements of the first microelectronic device being conductively bonded to at least one of the first or second conductive elements of the second microelectronic device to provide an electrically conductive path therebetween.

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