Barrier for through-silicon via

• US 8,680,682 B2
• Filed: 12/28/2012
• Issued: 03/25/2014
• Est. Priority Date: 03/23/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chiou, Wen-Chih, Wu, Weng-Jin
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US13/730,162
• Publication Number:
  US 20130113105A1
• Time in Patent Office: 452 Days
• Field of Search: 257/741, 257/751, 257/763, 257/773, 257/E21.171, 257/E21.175, 257/E21.575, 257/E21.584, 438/618, 438/627, 438/653, 438/656
• US Class Current: 257/773
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).

Claims

1. A semiconductor device comprising:

a semiconductor substrate having an opening defined by sidewalls;

a barrier layer disposed along the sidewalls of the opening, the barrier layer including a metal component and an alloying material, wherein the alloying material is less than approximately 15% of the barrier layer; and

a conductive material formed on the barrier layer and filling the opening, the conductive material to form a via.

2. The semiconductor device of claim 1, wherein the via is a through substrate via.

3. The semiconductor device of claim 1, wherein the metal component of the barrier layer is selected from the group consisting of Ta, TaN, Ti, TiN, and combinations thereof.

4. The semiconductor device of claim 1, wherein the alloying material is fluorine and the content of fluorine is less than approximately 5% of the barrier layer.

5. The semiconductor device of claim 1, wherein the alloying material is carbon and the content of carbon is less than approximately 5% of the barrier layer.

6. A semiconductor device comprising:

a semiconductor substrate having an opening;

a barrier layer on sidewalls of the opening, wherein the barrier layer has a first surface and an opposing second surface, and wherein the barrier layer includes a composition having a metal component and a fluorine alloying material from the first surface to the second surface; and

a conductive material formed on the barrier layer and filling the opening, the conductive material extending from a front surface of the semiconductor substrate to a back surface of the semiconductor substrate.

7. The semiconductor device of claim 6, wherein the content of fluorine of the fluorine alloying material is no more than about 15% of the barrier layer.

8. The semiconductor device of claim 6, further comprising:

a liner formed along sidewalls of the opening, the liner comprising a dielectric material.

9. The semiconductor device of claim 8, wherein the liner comprises an oxide layer or a silicon nitride layer.

10. The semiconductor device of claim 8, further comprising an adhesion layer between the barrier layer and the liner.

11. The semiconductor device of claim 6, further comprising an adhesion layer between the barrier layer and the conductive material layer.

12. The semiconductor device of claim 11, wherein the adhesion layer comprises Ta or TaN.

13. The semiconductor device of claim 6, wherein the barrier layer comprises tantalum nitride, tantalum, titanium, titanium nitride or combinations thereof.

14. A method of manufacturing a semiconductor device comprising:

providing a substrate with an opening located therein;

forming a dielectric liner along sidewalls of the opening;

forming a barrier layer over the liner and along the sidewalls and a bottom of the opening using a deposition process wherein the deposition process includes depositing a metal component while introducing an alloying material into the barrier layer during the deposition process, wherein the alloying material comprises fluorine, with a content of not more than about 15%;

forming a conductive material on the barrier layer having the metal component and the alloying material, wherein the forming the conductive material includes filling the opening; and

removing a portion of the substrate to expose the conductive material.

15. The method of claim 14, further comprising:

forming an adhesion layer on the barrier layer prior to the forming the conductive material.

16. The method of claim 14, further comprising:

forming a seed layer including at least one of manganese and aluminum on the barrier layer and underlying the conductive material.

17. The method of claim 14, further comprising:

forming an adhesion layer along the sidewalls and bottom of the opening prior to the forming the barrier layer.

18. The method of claim 14, wherein the barrier layer comprises tantalum nitride, tantalum, titanium, titanium nitride or combinations thereof.

19. The method of claim 14, wherein the content of fluorine in the barrier layer is less than approximately 5 percent.

20. The method of claim 14, wherein the deposition process is an atomic layer deposition (ALD).