Bond wire arrangement for efficient signal transmission

• US 8,680,690 B1
• Filed: 12/07/2012
• Issued: 03/25/2014
• Est. Priority Date: 12/07/2012
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Steeneken, Peter, Shrestha, Rameswor, Bredius, Martijn
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Schoenholtz, Joseph
• Application Number:
  US13/708,117
• Time in Patent Office: 473 Days
• Field of Search: None
• US Class Current: 257/784
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2223/6638 Differential pair signal lines
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48011 Length
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49052 Different loop heights
• CPC Class Codes: H01L 2224/4909 Loop shape arrangement
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/0272 : Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0274 : Arrangements for ensuring balanced coupling

Abstract

In one embodiment, a device includes a first IC having a differential signal driver and a first isolation circuit configured to provide differential signals transmitted by the differential signal driver to a first pair of bond pads of the first IC. First and second bond wires are configured to provide differential signals from the first pair of bond pads to a second pair of bond pad included in a second IC. The second IC includes a second isolation circuit configured to provide differential signals from the second pair of bond pads to a differential receiver circuit of the second IC. The bond wires are specifically arranged such that a distance between the first and second bond wires varies by at least 10% as measured at two points along a length of the first bond wire.

Claims

1. A device communicating using differential signaling and capacitive isolation between two integrated circuit chips, the device being subject to signal degradation from capacitance between bond wires connecting the two integrated circuit chips, the device comprising:

a first integrated circuit chip including;

a first differential signal driver circuit configured and arranged to transmit a first differential signal,

a first isolation circuit configured and arranged to receive the first differential signal and to produce a second version of the first differential signal that is isolated from the first differential signal driver circuit, and

a first pair of bond pads configured and arranged to receive the second version of the first differential signal;

a second integrated circuit chip including;

a second pair of bond pads configured and arranged to receive the second version of the first differential signal,

a second isolation circuit configured and arranged to receive the second version of the first differential signal and to produce a third version of the first differential signal that is isolated from the second pair of bond pads, and

a first differential signal receiver circuit configured and arranged to receive the third version of the first differential signal; and

first and second bond wires that each form an electrical connection between a respective one of the first pair of bond pads and a respective one of the second pair of bond pads, the first and second bond wires specifically arranged such that a distance between the first and second bond wires varies by at least 10% as measured at two points along a length of the first bond wire.

2. The device of claim 1, wherein the first bond wire has a height profile between the first pair of bond pads and the second pair of bond pads that is different than a height profile of the second bond wire between the first pair of bond pads and the second pair of bond pads.

3. The device of claim 2, wherein:

the first bond wire is positioned at a first height at a distance t, relative to a first end of the first bond wire; and

the second bond wire is positioned at a second height at the distance t, relative to a first end of the second bond wire and along a length of the second bond wire, the first height being different from the second height.

4. The device of claim 2, wherein the first and second bond wires are positioned in respective parallel planes that are each perpendicular to a surface of the first integrated circuit chip.

5. The device of claim 1, wherein the length of the first bond wire is different than a length of the second bond wire.

6. The device of claim 1, wherein the length of the first bond wire is the same as a length of the second bond wire.

7. The device of claim 1, wherein

bonds pads in the first pair of bond pad are separated by a distance that is less than 10 times a radius of the bond wires.

8. The device of claim 1, wherein:

the first isolation circuit includes;

a first isolation capacitor having a first plate coupled to a first output of the first differential signal driver circuit and a second plate coupled to a first one of the first pair of bond pads; and

a second isolation capacitor having a first plate coupled to a second output of the first differential signal driver circuit and a second plate coupled to a second one of the first pair of bond pads; and

the second isolation circuits includes;

a third isolation capacitor having a first plate coupled to a first input of the first differential signal receiver circuit and a second plate coupled to a first one of the second pair of bond pads; and

a fourth isolation capacitor having a first plate coupled to a second input of the first differential signal receiver circuit and a second plate coupled to a second one of the second pair of bond pads.

9. The device of claim 8, wherein the first, second, third, and fourth isolation capacitors have respective capacitances less than 100 fF.

10. The device of claim 8, wherein the first, second, third, and fourth isolation capacitors each have a dielectric made of silicon oxide.

11. The device of claim 10, wherein the dielectric of the first, second, third, and fourth isolation capacitors is thicker than 4 μ

m.

12. The device of claim 1, wherein the first and second isolation circuits each comprise an inductor.

13. The device of claim 1, further comprising:

an inductor having a first end coupled to the first bond wire and a second end coupled to the second bond wire.

14. The device of claim 13, wherein:

the first differential signal is a differential signal having a frequency F;

the first and second bond wires have a mutual capacitance C; and

the inductor has an inductance L, where L≈

1/[C*(2π

F)²].

15. The device of claim 1, wherein:

the second integrated circuit chip further includes;

a second differential signal driver circuit configured and arranged to transmit a second differential signal;

a third isolation circuit configured and arranged to receive the second differential signal and to produce a second version of the second differential signal that is capacitively isolated from the second differential signal driver circuit; and

a third pair of bond pads configured and arranged to receive the second version of the second differential signal; and

the first integrated circuit chip further includes;

a fourth pair of bond pads configured and arranged to receive the second version of the second differential signal;

a fourth isolation circuit configured and arranged to receive the second version of the second differential signal and to produce a third version of the second differential signal that is capacitively isolated from the fourth pair of bond pads; and

a second differential signal receiver circuit configured and arranged to receive the third version of a second differential signal; and

third and fourth bond wires that each form an electrical connection between a respective one of the third pair of bond pads and a respective one of the fourth pair of bond pads, the third and fourth bond wires specifically arranged such that a distance between the third and fourth bond wires varies by at least 10% as measured at two points along a length of the third bond wire.

16. The device of claim 15, wherein:

the first integrated circuit chip further includes a first capacitor having a first terminal coupled to one of the first pair of bond pads and a second terminal coupled to a bond pad of the fourth pair of bond pads and a second capacitor having a first terminal coupled to one of the second pair of bond pads and a second terminal coupled to a bond pad of the third pair of bond pads.

17. A device, comprising:

a first integrated circuit (IC) including;

a first differential signal driver circuit;

a first differential receiver circuit;

first, second, third, and fourth bond pads;

a first isolation circuit configured and arranged to provide differential signals from first and second outputs of the first differential signal driver circuit to the first and second bond pads and provide isolation between the first differential signal driver circuit and the first and second bond pads; and

a second isolation circuit configured and arranged to provide differential signals from the third and fourth bond pads to first and second inputs of the first differential receiver circuit and provide isolation between the first differential receiver circuit and the third and fourth bond pads;

first, second, third, and fourth bond wires respectively coupled to the first, second, third, and fourth bond pads, the second bond wire being adjacent to the third bond wire;

a second IC including;

a second differential signal driver circuit;

a second differential receiver circuit;

fifth, sixth, seventh, and eighth bond pads respectively coupled to the first, second, third, and fourth bond pads;

a third isolation circuit configured and arranged to provide differential signals from the fifth and sixth bond pads to first and second inputs of the second differential receiver circuit and isolation between the second differential receiver circuit and the fifth and sixth bond pads; and

a fourth isolation circuit configured and arranged to provide differential signals from first and second outputs of the second differential signal driver circuit to the seventh and eights bond pads and provide isolation between the second differential signal driver circuit and the seventh and eighth bond pads; and

a balancing circuit, configured to provide a capacitance between the first and fourth bond wires that is substantially equal to the parasitic capacitance between the adjacent second and third bond wires.

18. The device of claim 17, wherein the balancing circuit includes a capacitor having a first plate coupled to the first bond wire and a second plate coupled to the fourth bond wire.

19. The device of claim 17, wherein each adjacent pair of the first, second, third, and fourth bond wires are specifically arranged such that a distance between the adjacent pair of bond wires varies by at least 10% as measured at two points along a length of one of the adjacent pair of bond wires.

20. A method of manufacturing a device that communicates differential signals between first and second integrated circuits (ICs), which operate in respective voltage domains, over a pair of bond wires, comprising:

manufacturing first and second bond wires of the pair of bond wires, each having a respective height profile extending between first and second ends of the bond wire;

placing the first bond wire to have a first end of the bond wire coupled to a first bond pad located on the first IC and a second end of the bond wire coupled to a second bond pad located on the second IC; and

placing the second bond wire to have a first end of the bond wire coupled to a third bond pad located on the first IC and a second end of the bond wire coupled to a fourth bond pad located on the second IC, wherein the first and second bond wires are oriented such that a distance between the first and second bond wires varies by at least 10% as measured at two points along a length of the first bond wire.