Self-initializing on-chip data processing apparatus and method of self-initializing an on-chip data processing apparatus

• US 8,680,900 B2
• Filed: 08/10/2012
• Issued: 03/25/2014
• Est. Priority Date: 08/10/2012
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Wang, Bingda Brandon, Gitchev, Kostadin
• Primary Examiner(s): ROJAS, DANIEL E
• Application Number:
  US13/571,753
• Publication Number:
  US 20140043071A1
• Time in Patent Office: 592 Days
• Field of Search: 327/142
• US Class Current: 327/142
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

An on-chip data processing apparatus has an operating supply voltage selected from a range of supply voltages and has voltage level detection circuitry configured to determine the level of the operating supply voltage. The voltage level detection circuitry comprises adaptive circuitry responsive to a variation in the reference voltage. Phase lock loop circuitry is configured to generate a source clock signal from the operating supply voltage, to receive the voltage level selection signal, to select a target frequency for the source clock signal in dependence on the voltage level selection signal, and to phase lock the source clock signal on the target frequency. Initialization circuitry is configured to initialize the on-chip data processing apparatus for data processing in dependence on the level of said operating supply voltage after the phase lock loop circuitry has phase locked the source clock signal on the target frequency.

Claims

1. An on-chip data processing apparatus configured to use an operating supply voltage selected from a range of supply voltages, said on-chip data processing apparatus comprising:

voltage level detection circuitry configured to determine a level of said operating supply voltage within said range of supply voltages by comparison to a reference voltage and to generate a voltage level selection signal in dependence on a result of said comparison, wherein said voltage level detection circuitry comprises adaptive circuitry responsive to a variation in said reference voltage such that said determination of said level of said operating supply voltage is independent of said variation in said reference voltage;

phase lock loop circuitry configured to generate a source clock signal from said operating supply voltage, said phase lock loop circuitry configured to receive said voltage level selection signal, to select a target frequency for said source clock signal in dependence on said voltage level selection signal, and to phase lock said source clock signal on said target frequency; and

initialization circuitry configured to initialize said on-chip data processing apparatus for data processing in dependence on said level of said operating supply voltage with respect to said range of supply voltages after said phase lock loop circuitry has phase locked said source clock signal on said target frequency.

2. The on-chip data processing apparatus as claimed in claim 1, wherein said on-chip data processing apparatus comprises input-output circuitry configured to participate in data exchange with an off-chip destination, wherein said operating supply voltage is determined by a protocol used for said data exchange.

3. The on-chip data processing apparatus as claimed in claim 1, wherein said voltage level detection circuitry is configured to generate said voltage level selection signal as a digital value indicative of a selected sub-range within said range of supply voltages.

4. The on-chip data processing apparatus as claimed in claim 3, wherein said digital value is a binary value indicative of whether said level of said operating supply voltage is in a first sub-range of said range of supply voltages or is in a second sub-range of said range of supply voltages.

5. The on-chip data processing apparatus as claimed in claim 1, wherein said adaptive circuitry comprises a self-biasing feedback circuitry.

6. The on-chip data processing apparatus as claimed in claim 1, wherein said voltage level detection circuitry comprises a threshold device configured to generate said voltage level selection signal, wherein an input voltage of said threshold device is dependent on an output of said adaptive circuitry.

7. The on-chip data processing apparatus as claimed in claim 6, wherein said threshold device is an inverter.

8. The on-chip data processing apparatus as claimed in claim 6, wherein said threshold device is a comparator.

9. The on-chip data processing apparatus as claimed in claim 1, wherein said voltage level detection circuitry is configured to generate at least one scaled down version of said operating supply voltage for comparison to said reference voltage.

10. The on-chip data processing apparatus as claimed in claim 9, wherein said at least one scaled version of said operating supply voltage is generated from a selected node of a chain of resistors.

11. The on-chip data processing apparatus as claimed in claim 2, wherein said initialization circuitry is configured to adapt a configuration of said input-output circuitry in dependence on said voltage level selection signal.

12. The on-chip data processing apparatus as claimed in claim 11, wherein said configuration determines a gain characteristic of said input-output circuitry, wherein said gain characteristic of said input-output circuitry is dependent on said operating supply voltage.

13. The on-chip data processing apparatus as claimed in claim 11, wherein said configuration determines a power consumption characteristic of said input-output circuitry.

14. The on-chip data processing apparatus as claimed in claim 11, wherein said configuration determines an operational frequency characteristic of said input-output circuitry.

15. The on-chip data processing apparatus as claimed in claim 2, wherein said on-chip data processing apparatus is a DDR PHY component.

16. The on-chip data processing apparatus as claimed in claim 15, wherein said data exchange takes place in accordance with a JEDEC-defined DDR standard, wherein said JEDEC-defined DDR standard defines said level of said operating supply voltage.

17. The on-chip data processing apparatus as claimed in claim 2, wherein said off-chip destination is a DRAM memory device.

18. An on-chip data processing apparatus configured to use an operating supply voltage selected from a range of supply voltages, said on-chip data processing apparatus comprising:

voltage level detection means for determining a level of said operating supply voltage within said range of supply voltages by comparison to a reference voltage and to generate a voltage level selection signal in dependence on a result of said comparison, wherein said voltage level detection means comprises adaptive means for responding to a variation in said reference voltage such that said determination of said level of said operating supply voltage is independent of said variation in said reference voltage;

phase lock loop means for generating a source clock signal from said operating supply voltage, said phase lock loop circuitry configured to receive said voltage level selection signal, to select a target frequency for said source clock signal in dependence on said voltage level selection signal, and to phase lock said source clock signal on said target frequency; and

initialization means for initializing said on-chip data processing apparatus for data processing in dependence on said level of said operating supply voltage with respect to said range of supply voltages after said phase lock loop means has phase locked said source clock signal on said target frequency.

19. A method of initializing an on-chip data processing apparatus configured to use an operating supply voltage selected from a range of supply voltages, said method comprising the steps of:

determining a level of said operating supply voltage within said range of supply voltages by comparison to a reference voltage and to generate a voltage level selection signal in dependence on a result of said comparison, wherein said determining comprises using adaptive circuitry responsive to a variation in said reference voltage such that said determining is independent of said variation in said reference voltage;

generating a source clock signal from said operating supply voltage by receiving said voltage level selection signal in phase lock loop circuitry, selecting a target frequency for said source clock signal in dependence on said voltage level selection signal, and phase locking said source clock signal on said target frequency; and

initializing said on-chip data processing apparatus for data processing in dependence on said level of said operating supply voltage with respect to said range of supply voltages after said phase locking of said source clock signal on said target frequency has been established.