Apparatus and method for equalization
First Claim
1. An apparatus, comprising:
- a capacitor block having a first terminal and a second terminal;
a first resistor having a first end and a second end, the first end configured to receive a first input voltage of a differential input voltage;
a second resistor having a first end electrically connected to the second end of the first resistor at a first output node;
a third resistor having a first end and a second end, the first end configured to receive a second input voltage of the differential input voltage, the third resistor having a resistance equal to about that of the first resistor;
a fourth resistor having a first end electrically connected to the second end of the third resistor at a second output node, the fourth resistor having a resistance equal to about that of the second resistor;
a first transconductance buffer configured to receive the first input voltage and to generate a first current from the second output node to the first terminal of the capacitor block, the first current proportional to about the first input voltage; and
a second transconductance buffer configured to receive the second input voltage and to generate a second current from the first output node to the second terminal of the capacitor block, the second current proportional to about the second input voltage,wherein the first and second output nodes are configured to provide a first differential output.
1 Assignment
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Accused Products
Abstract
Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor.
4 Citations
23 Claims
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1. An apparatus, comprising:
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a capacitor block having a first terminal and a second terminal; a first resistor having a first end and a second end, the first end configured to receive a first input voltage of a differential input voltage; a second resistor having a first end electrically connected to the second end of the first resistor at a first output node; a third resistor having a first end and a second end, the first end configured to receive a second input voltage of the differential input voltage, the third resistor having a resistance equal to about that of the first resistor; a fourth resistor having a first end electrically connected to the second end of the third resistor at a second output node, the fourth resistor having a resistance equal to about that of the second resistor; a first transconductance buffer configured to receive the first input voltage and to generate a first current from the second output node to the first terminal of the capacitor block, the first current proportional to about the first input voltage; and a second transconductance buffer configured to receive the second input voltage and to generate a second current from the first output node to the second terminal of the capacitor block, the second current proportional to about the second input voltage, wherein the first and second output nodes are configured to provide a first differential output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification