Memory circuit, signal processing circuit, and electronic device

• US 8,681,533 B2
• Filed: 04/23/2012
• Issued: 03/25/2014
• Est. Priority Date: 04/28/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fujita, Masashi
• Primary Examiner(s): King, Douglas
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US13/453,135
• Publication Number:
  US 20120274378A1
• Time in Patent Office: 701 Days
• Field of Search: 365/149, 365/174, 365/188, 365/189.15, 326/102
• US Class Current: 365/149
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Abstract

A signal processing circuit using a nonvolatile memory circuit with a novel structure is provided. The nonvolatile memory circuit is formed using a transistor including an oxide semiconductor and a capacitor connected to one of a source electrode and a drain electrode of the transistor. A high-level potential is written to the memory circuit in advance, and this state is kept in the case where data to be saved has a high-level potential, whereas a low-level potential is written to the memory circuit in the case where data to be saved has a low-level potential. Thus, a signal processing circuit with improved writing speed can be provided.

Claims

1. A memory circuit comprising:

a first circuit comprising at least two input terminals and at least one output terminal;

a second circuit comprising at least two input terminals and at least one output terminal;

a third circuit comprising at least two input terminals and at least one output terminal;

a first switch;

a first transistor comprising an oxide semiconductor;

a first capacitor;

a first inverter; and

a second inverter,

wherein one of the input terminals of the first circuit is configured to be supplied with a reading signal, the other of the input terminals of the first circuit is electrically connected to one of a source electrode and a drain electrode of the first transistor, and the output terminal of the first circuit is electrically connected to an input terminal of the first switch,

wherein one of the input terminals of the second circuit is configured to be supplied with the reading signal, the other of the input terminals of the second circuit is electrically connected to an output terminal of the first switch, and the output terminal of the second circuit is electrically connected to the other of the source electrode and the drain electrode of the first transistor,

wherein one of the input terminals of the third circuit is electrically connected to an output terminal of the first inverter, the other of the input terminals of the third circuit is configured to be supplied with the reading signal, the output terminal of the third circuit is electrically connected to an input terminal of the second inverter and a first control terminal of the first switch, and an output terminal of the second inverter is electrically connected to a second control terminal of the first switch,

wherein a gate electrode of the first transistor is configured to be supplied with a control signal,

wherein an input terminal of the first inverter is configured to be supplied with the control signal,

wherein one of electrodes of the first capacitor is electrically connected to the one of the source electrode and the drain electrode of the first transistor, and the other of the electrodes of the first capacitor is grounded,

wherein a low-level potential is supplied to either of the input terminals of the second circuit before supply of a power supply voltage is stopped, and

wherein a high-level potential is supplied between the other of the source electrode and the drain electrode of the first transistor and the first capacitor.

2. The memory circuit according to claim 1,

wherein the oxide semiconductor comprises In, Ga, and Zn.

3. The memory circuit according to claim 1,

wherein the first circuit comprises a second transistor, a third transistor, a fourth transistor, and a fifth transistor,

wherein one of a source electrode and a drain electrode of the second transistor is configured to be supplied with a power supply potential,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor,

wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor,

wherein the other of the source electrode and the drain electrode of the fourth transistor is grounded,

wherein a gate electrode of the second transistor and a gate electrode of the third transistor are configured to be supplied with the reading signal,

wherein one of a source electrode and a drain electrode of the fifth transistor is configured to be supplied with the power supply potential,

wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the other of the source electrode and the drain electrode of the second transistor,

wherein a gate electrode of the fifth transistor is electrically connected to a gate electrode of the fourth transistor, and

wherein the one of the source electrode and the drain electrode of the first transistor is electrically connected to the gate electrode of the fourth transistor.

4. The memory circuit according to claim 1,

wherein the first circuit comprises a second transistor, a third transistor, a fourth transistor, and a second capacitor,

wherein one of a source electrode and a drain electrode of the second transistor is configured to be supplied with a power supply potential,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor,

wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor,

wherein the other of the source electrode and the drain electrode of the fourth transistor is grounded,

wherein a gate electrode of the second transistor and a gate electrode of the third transistor are configured to be supplied with the reading signal,

wherein one of electrodes of the second capacitor is electrically connected to the other of the source electrode and the drain electrode of the second transistor,

wherein the other of the electrodes of the second capacitor is grounded, and

wherein the one of the source electrode and the drain electrode of the first transistor is electrically connected to a gate electrode of the fourth transistor.

5. An electronic device comprising the memory circuit according to claim 1.

6. A signal processing circuit comprising:

the memory circuit according to claim 1;

a second switch;

a third inverter;

a third switch;

a fourth inverter;

a fourth switch;

a fifth inverter; and

a sixth inverter,

wherein an input terminal of the second switch is configured to be supplied with an input signal, and an output terminal of the second switch is electrically connected to an input terminal of the third inverter and an output terminal of the fourth inverter,

wherein an output terminal of the third inverter is electrically connected to an input terminal of the third switch,

wherein an output terminal of the third switch is electrically connected to an input terminal of the fourth inverter and an input terminal of the fourth switch,

wherein an output terminal of the fourth switch is electrically connected to an input terminal of the fifth inverter and an output terminal of the sixth inverter,

wherein an output terminal of the fifth inverter is electrically connected to an input terminal of the sixth inverter, and

wherein the memory circuit is electrically connected to the third switch.

7. An electronic device comprising the signal processing circuit according to claim 6.