Memory with correlated resistance

• US 8,681,557 B2
• Filed: 09/12/2012
• Issued: 03/25/2014
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Baker, R. Jacob
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/612,408
• Publication Number:
  US 20130003472A1
• Time in Patent Office: 559 Days
• Field of Search: 365/185.17, 365/185.09, 365/185.29, 365/230.03
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices

Abstract

Methods, systems, and devices include a system for sequentially writing to a data locations coupled to one another in series. The system includes a plurality of data locations and a controller. The controller is configured to sequentially write data values to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location.

Claims

1. A method, comprising:

writing to each of a plurality of floating gate transistors one at a time, in sequence, starting with a first floating gate transistor at an end of the series and finishing with a second floating gate transistor at the other end of the series, wherein writing comprises incrementally adjusting a charge on each of the floating gate transistors and sensing whether the charge corresponds to a desired value.

2. The method of claim 1, comprising erasing the plurality of floating gate transistors generally simultaneously.

3. The method of claim 1, comprising reading from one of the plurality of floating gate transistors, wherein reading is performed before any of the floating gate transistors is written to again.

4. The method of claim 1, comprising reading from one of the plurality of floating gate transistors with a delta-sigma modulator.

5. The method of claim 4, wherein reading comprises transmitting a bit-stream from the delta-sigma modulator to a counter.

6. The method of claim 4, wherein reading comprises truncating a least significant bit from an output of the counter.

7. A method, comprising:

writing a plurality of data values to a plurality of data locations one at a time, in sequence, wherein the writing comprises;

adjusting a parameter of one of the data locations by an increment;

reading the value stored by the one of the data locations;

determining whether the value stored corresponds to a value to be written; and

if the value stored does not correspond to the value to be written, adjusting the parameter by another increment.

8. The method of claim 7, wherein adjusting the parameter comprises changing a charge on the one of the data locations.

9. The method of claim 7, wherein adjusting the parameter comprises adjusting the crystallinity of the one of the data locations.

10. The method of claim 7, wherein writing the plurality of data values to the plurality of data locations one at a time, in sequence, comprises starting with a data location at an end of the series and sequentially writing to each adjacent data location.

11. The method of claim 10, wherein starting with the data location at an end of the series comprises starting with a data location with its source on a distal end of the series.

12. The method of claim 10, wherein starting with the data location at an end of the series comprises starting with a data location with its drain on a distal end of the series.

13. The method of claim 7, wherein writing the plurality of data values to the plurality of data locations comprises writing the plurality of data values to a plurality of floating gate transistors.

14. The method of claim 7, wherein writing the plurality of data values to the plurality of data locations comprises writing the plurality of data values to a plurality of phase change memory elements.

15. A method, comprising:

writing to each of a plurality of data locations starting with a data location at an end of the plurality of data locations and then sequentially writing to each adjacent data location; and

reading from one of the data locations by sensing a current through the data location with a delta-sigma modulator.

16. The method of claim 15, wherein writing comprises writing to every data location transistor in the plurality of data locations based on a number of data locations between a given data location and a data location at the end of the plurality of data locations.

17. The method of claim 15, wherein writing comprises:

adjusting a parameter of one of the data locations by an increment;

reading the value stored by the one of the data locations;

determining whether the value stored corresponds to a value to be written; and

if the value stored does not correspond to the value to be written, adjusting the parameter by another increment.

18. The method of claim 17, wherein reading comprises sensing a current through the one of the data locations with the delta-sigma modulator.

19. The method of claim 15, comprising erasing the plurality of data locations generally simultaneously.

20. The method of claim 15, comprising transmitting data read from the one of the data locations to a processor of a computer system.