Clock offset compensator

• US 8,681,914 B2
• Filed: 08/28/2007
• Issued: 03/25/2014
• Est. Priority Date: 10/09/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutioso, Henri, Wu, Lei
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US11/895,974
• Publication Number:
  US 20070297553A1
• Time in Patent Office: 2,401 Days
• Field of Search: 375/373, 375/232, 375/377, 375/144, 375219-222, 375/268, 375/271, 375/326, 375/327, 375/356, 375/358, 375/362, 375/371, 375/376, 370/286, 327144-147, 327/155, 327/156
• US Class Current: 375/358
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A device comprises a transmitter, a receiver and a clock generator that generates a clock signal having a local clock phase. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from a host by the receiver. A frequency offset circuit communicates with the clock recovery circuit and the clock generator and generates a frequency offset based on the local clock phase and the recovered host clock frequency. A frequency compensator compensates a frequency of the transmitter using the frequency offset.

Claims

1. A device comprising:

a receiver configured to receive data from a host;

a clock generator configured to generate a clock signal having a local clock phase;

a clock recovery circuit in communication with the receiver, wherein the clock recovery circuit is configured to recover a host clock frequency from the data received by the receiver from the host;

a frequency offset circuit in communication with each of the clock recovery circuit and the clock generator, wherein the frequency offset circuit is configured to generate a frequency offset based on the local clock phase and the host clock frequency recovered by the clock recovery circuit; and

a frequency compensator configured to

i) generate a spread spectrum modulation signal when spread spectrum operation is enabled,

ii) generate a constant signal when the spread spectrum operation is disabled, and

iii) compensate a frequency of a transmitter using the frequency offset and a selected one of the spread spectrum modulation signal and the constant signal, wherein the device is configured to transmit data back to the host based on the compensated frequency.

2. The device of claim 1, wherein the frequency compensator includes a low pass filter in communication with the frequency offset circuit.

3. The device of claim 2, wherein the frequency compensator further includes an accumulator in communication with the low pass filter, wherein the accumulator is configured to generate a phase offset.

4. The device of claim 3, wherein the frequency compensator further includes an interpolator configured to i) receive the local clock phase from the clock generator and the phase offset from the accumulator and ii) output a compensated clock signal to the transmitter.

5. The device of claim 1, wherein the clock generator includes a phase-locked loop circuit that includes:

a reference frequency generator;

a phase detector in communication with the reference frequency generator;

a low pass filter in communication with the phase detector; and

a voltage controlled oscillator in communication with the low pass filter.

6. The device of claim 5, wherein the reference frequency generator comprises a crystal resonator or a ceramic resonator.

7. The device of claim 5, wherein the phase-locked loop circuit further includes:

a 1/N divider having (i) an input in communication with the voltage controlled oscillator and (ii) an output in communication with the phase detector; and

a 1/M divider having (i) an input in communication with the reference frequency generator and (ii) an output in communication with the phase detector, wherein N and M are adjusted to create the spread spectrum modulation signal when the spread spectrum operation is enabled.

8. The device of claim 7, wherein the phase-locked loop further includes an interpolator in communication with (i) an output of the voltage controlled oscillator and (ii) an input of the 1/N divider.

9. The device of claim 1, wherein the host and the device are configured to communicate using a serial advanced technology attachment (SATA) standard.

10. The device of claim 1, wherein the host is a disk controller and the device is a disk drive.

11. A communication system, comprising:

a host including i) a host transmitter, ii) a host receiver, and iii) a host clock generator configured to generate a host clock frequency; and

a device in communication with the host using a serial advanced technology attachment (SATA) standard, the device including;

a device transmitter;

a device receiver;

a device clock generator configured to generate a clock signal having a local clock phase;

a clock recovery circuit configured to recover the host clock frequency from data received by the device receiver from the host;

a frequency offset circuit configured to generate a frequency offset based on the local clock phase and the recovered host clock frequency recovered by the clock recovery circuit; and

a frequency compensator configured to i) generate a spread spectrum modulation signal when spread spectrum operation is enabled, ii) generate a constant signal when spread spectrum operation is disabled, and iii) compensate a frequency of the device transmitter using the frequency offset and a selected one of the spread spectrum modulation signal and the constant signal, wherein the device is configured to transmit data back to the host based on the compensated frequency.

12. The communication system of claim 11, wherein the frequency compensator includes a low pass filter in communication with the frequency offset circuit.

13. The communication system of claim 12, wherein the frequency compensator further includes an accumulator in communication with the low pass filter, wherein the accumulator is configured to generate a phase offset.

14. The communication system of claim 13, wherein the frequency compensator further includes an interpolator configured to receive i) the local clock phase from the device clock generator and ii) the phase offset from the accumulator.

15. The communication system of claim 11, wherein the device clock generator includes a phase-locked loop circuit that includes:

a reference frequency generator;

a phase detector in communication with the reference frequency generator;

a low pass filter in communication with the phase detector; and

a voltage controlled oscillator in communication with the low pass filter.

16. The communication system of claim 15, wherein the reference frequency generator comprises a crystal resonator or a ceramic resonator.

17. The communication system of claim 15, wherein the phase-locked loop circuit further includes:

a 1/N divider having an input in communication with the voltage controlled oscillator and an output in communication with the phase detector, and

a 1/M divider having an input in communication with the reference frequency generator and an output in communication with the phase detector, wherein N and M are adjusted to create the spread spectrum modulation signal when the spread spectrum operation is enabled.

18. The communication system of claim 17, wherein the phase-locked loop circuit further includes an interpolator in communication with an output of the voltage controlled oscillator and an input of the 1/N divider.

19. The communication system of claim 11, wherein the host is a disk controller and the device is a disk drive.

20. A method for transmitting/receiving data in a device, the method comprising:

transmitting data to a host;

receiving data from the host;

generating a clock signal having a local clock phase;

recovering a host clock frequency from data received by the device from the host;

generating a frequency offset based on the local clock phase and the recovered host clock frequency;

generating a spread spectrum modulation signal when spread spectrum operation is enabled;

generating a constant signal when the spread spectrum operation is disabled,

compensating a transmitting frequency using the frequency offset and a selected one of the spread spectrum modulation signal and the constant signal; and

transmitting the data back to the host from the device based on the compensated transmitting frequency.

21. The method of claim 20, further comprising low pass filtering the frequency offset.

22. The method of claim 21, further comprising generating a phase offset from the filtered frequency offset.

23. The method of claim 22, further comprising generating a compensated clock signal for transmitting the data to the host based on the local clock phase and the phase offset.

24. The method of claim 20, wherein the local clock phase is generated by a phase-locked loop circuit.

25. The method of claim 24, wherein the phase-locked loop circuit receives a reference frequency generated by at least one of a crystal resonator and a ceramic resonator.