Synchronous transfer of streaming data in a distributed antenna system

• US 8,681,917 B2
• Filed: 03/30/2011
• Issued: 03/25/2014
• Est. Priority Date: 03/31/2010
• Status: Active Grant

• Current Assignee: CommScope Technologies, LLC (CommScope Holding Company, Inc.)
• Original Assignee: Andrew LLC (CommScope Holding Company, Inc.)
• Inventors: McAllister, Donald, Ranson, Chris, Phillips, Fred William
• Primary Examiner(s): Torres, Juan A
• Application Number:
  US13/076,002
• Publication Number:
  US 20110243291A1
• Time in Patent Office: 1,091 Days
• Field of Search: 375/371, 375/376
• US Class Current: 375/371
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04L 1/0625 Transmitter arrangements
• CPC Class Codes: H04L 1/0631 Receiver arrangements
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04W 88/085 Access point devices with remote components

Abstract

Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium. The method comprises receiving a modulated signal that includes the encoded binary data stream and extracting the encoded binary data stream. The method further comprises generating a recovered clock signal that is phase locked to the encoded binary data stream, generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal, and integrating the error signal to generate a signal to control a voltage controlled oscillator. The method further comprises generating a stable recovered clock signal and producing at least one output clock by scaling the stable recovered clock signal frequency.

Claims

1. A method of generating a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium, the method comprising:

receiving a modulated signal that includes the encoded binary data stream via high speed data interface circuitry;

extracting the encoded binary data stream from the modulated signal;

generating a recovered clock signal that is phase locked to the encoded binary data stream with circuitry having a phase-locked loop that includes a loop filter configured with a bandwidth that does not substantially block the long-term drift in the modulated signal;

generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal;

integrating the error signal with the loop filter configured with a bandwidth that allows the jitter and drift in the encoded binary data stream to generate a signal to control a voltage controlled oscillator;

generating a stable recovered clock signal by filtering the recovered clock signal using a filtering circuit having a bandwidth narrower than the bandwidth of the circuitry that is used for generating the recovered clock signal to remove jitter without substantially affecting the frequency of the stable recovered clock signal to allow the stable recovered clock signal to track drift of the encoded binary data stream; and

producing at least one output clock by scaling the stable recovered clock signal frequency.

2. The method of claim 1, wherein the high speed data interface circuitry includes at least a one gigabit per second (Gbps) Ethernet interface.

3. The method of claim 1, wherein the communication medium is a communication cable having at least one twisted pair cable.

4. The method of claim 2, wherein the Ethernet interface is synchronous or asynchronous.

5. A remote unit for a distributed antenna system, comprising:

high speed data interface circuitry for communicating with a master unit;

RF transceiver circuitry for communicating with a subscriber unit;

a processing unit that multiplexes and routes data to the high speed data interface and that de-multiplexes and routes data from the high speed data interface circuitry to the RF transceiver circuitry;

a clock recovery circuit that includes a phase-locked loop, the phase-locked loop including a loop filter having a bandwidth that does not substantially block the jitter or long-term drift in a modulated signal, the clock recovery circuit configured to receive the modulated signal from the high speed data interface circuitry that includes a serial encoded binary data stream and further configured to generate a recovered clock signal therefrom;

a filtering circuit having a bandwidth narrower than the bandwidth of the filter of the clock recovery circuit and that is configured to filter the recovered clock signal to remove jitter without removing long-term drift in the modulated signal to generate a stable recovered clock signal; and

a scaling circuit configured to scale the frequency of the stable recovered clock signal to generate at least one output signal at a respective predetermined target frequency.

6. The remote unit of claim 5, wherein the high speed data interface circuitry is coupled to a communication medium having at least one twisted pair cable.

7. The remote unit of claim 5, wherein the data that is multiplexed and routed to the high speed data interface circuitry includes at least one of digitized RF cellular voice data, digitized RF non-cellular voice data, digitized RF cellular data, digitized RF non-cellular data, control data, maintenance data, Ethernet data, or WiFi data.

8. The remote unit of claim 5, wherein the processing unit is configured to adjust the rate or the content of data being transmitted on the high speed data link to match the capability of that link by excluding low priority data from the multiplexed stream.

9. The remote unit of claim 5, wherein the RF transceiver circuitry is configured to communicate cellular data with the subscriber unit.

10. The remote unit of claim 5, further comprising:

an auxiliary interface for at least one of communicating control data, maintenance data, Ethernet data, or WiFi data.

11. The remote unit of claim 9, wherein the RF transceiver circuitry is further configured to communicate non-cellular data with the subscriber unit.

12. A distributed antenna system, comprising:

a master unit that clocks an encoded data stream onto high speed data interface circuitry via a modulated signal based upon an output of a reference oscillator; and

at least one remote unit that receives the modulated signal from the master unit, each remote unit including;

high speed data interface circuitry for receiving the modulated signal from the master unit,

a clock recovery circuit that includes a phase-locked loop, the phase-locked loop in turn including a loop filter configured with a bandwidth that does not substantially block the jitter or long-term drift in the modulated signal, the clock recovery circuit configured to generate a recovered clock signal from the modulated signal that includes the encoded data stream;

a filtering circuit having a bandwidth narrower than the bandwidth of the filter of the clock recovery circuit and that is configured to filter the recovered clock signal to remove jitter without removing long-term drift in the modulated signal and further configured to generate a stable recovered clock signal; and

a scaling circuit configured to scale the frequency of the stabled recovered clock signal to generate an output signal at a predetermined target frequency.

13. The system of claim 12, wherein the high speed data interface circuitry is coupled to a communication medium having at least one twisted pair cable.

14. The system of claim 12, further comprising:

an extension unit that relays the modulated signal from the master unit to the remote unit.

15. The system of claim 12, wherein the master unit further includes:

master unit RF transceiver circuitry for communication with a base transceiver station,

wherein the base transceiver station provides the master unit with cellular data and wherein the encoded data stream includes the cellular data.

16. The system of claim 12, the master unit RF transceiver circuitry is configured to communicate with a subscriber unit, wherein the master unit further includes:

master unit high speed data interface circuitry for communication with the at least one remote unit;

an auxiliary interface for communicating at least one of control data, maintenance data, Ethernet data, or WiFi data; and

a processor that multiplexes data from the master unit transceiver circuitry and the auxiliary interface for transmission to the at least one remote unit via the master unit high speed data interface circuitry, and that de-multiplexes data received from the master unit high speed data interface circuitry for transmission to the base transceiver station via the master unit RF transceiver circuitry.

17. The system of claim 12, wherein the high speed data interface circuitry is an at least a one gigabit per second (Gbps) Ethernet interface.

18. The system of claim 12, the remote unit further including:

RF transceiver circuitry for communicating with a subscriber unit; and

a processing unit that de-multiplexes data from the high speed data interface circuitry for transmission by the RF transceiver circuitry, and that multiplexes data from the RF transceiver circuitry for transmission by the high speed data interface circuitry,

wherein the processing unit is configured adjust the rate of data being transmitted on the high speed data interface to match the capability of that interface by excluding low priority data from the multiplexed stream.

19. The system of claim 12, the remote unit further including:

RF transceiver circuitry for communicating cellular and non-cellular data with a subscriber unit;

an auxiliary interface for communicating at least one of control data, maintenance data, Ethernet data, or WiFi data; and

a processing unit that de-multiplexes data from the high speed data interface circuitry for transmission by the RF transceiver circuitry or the auxiliary interface, and that multiplexes data from the RF transceiver circuitry and the auxiliary interface for transmission by the high speed data interface circuitry.

20. The system of claim 17, wherein the Ethernet interface is synchronous or asynchronous.

21. The system of claim 18, wherein the data that is multiplexed to the high speed data interface circuitry includes at least one of digitized RF cellular voice data, digitized RF non-cellular voice data, digitized RF cellular data, digitized RF non-cellular data, control data, maintenance data, or WiFi data.

22. A method of generating a jitter reduced clock signal from an encoded data stream, the method comprising:

generating a recovered clock signal based on the encoded data stream, the recovered clock signal being phase locked with circuitry having a phase-locked loop to an oscillator used to clock the encoded data stream onto a modulated signal, the phase-locked loop including a loop filter configured with a bandwidth that does not substantially block the long-term drift in the encoded data stream;

clocking data from the encoded data stream into a processing unit based on the recovered clock signal;

detecting a periodic signal component, other than the bit rate, of the encoded data stream with the processing unit;

generating a reference clock signal based on the detected periodic signal component;

filtering the reference clock signal with a circuit having a bandwidth narrower than the bandwidth of the circuitry that is used for generating the recovered clock signal and that substantially blocks jitter while substantially allowing long-term drift of the reference clock signal; and

scaling a frequency of the reference clock signal to generate at least one output signal at a predetermined target frequency.