Memory controller for sequentially prefetching data for a processor of a computer system

• US 8,683,132 B1
• Filed: 09/29/2003
• Issued: 03/25/2014
• Est. Priority Date: 09/29/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Danilak, Radoslav
• Primary Examiner(s): Rutz, Jared
• Application Number:
  US10/674,618
• Time in Patent Office: 3,830 Days
• Field of Search: 711/119, 711/137
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch

Abstract

A memory controller for prefetching data for a processor, or CPU, of a computer system. The memory controller functions by interfacing the processor to system memory via a system memory bus. A prefetch cache is included in the memory controller. The prefetch cache includes a short-term storage portion and a long-term storage portion. The prefetch cache is configured to access system memory to retrieve and store a plurality of sequential cache lines subsequent to a processor access to system memory.

Claims

1. A device for prefetching data for a processor of a computer system, comprising:

a memory controller for interfacing the processor to system memory via a system memory bus; and

a prefetch cache having a short-term storage portion and a long-term storage portion included in the memory controller, the prefetch cache configured to access said system memory to retrieve and store a plurality of sequential cache lines subsequent to a processor access to said system memory, wherein the memory controller is configured to track memory accesses by a CPU to said system memory and is configured to interrupt a prefetch access to system memory upon detection of a CPU access to said system memory, wherein the short-term storage portion is configured to initially store the sequential cache lines, wherein a plurality of non-hit cache lines are transferred from the short-term storage portion to the long-term storage portion to retain the plurality of non-hit cache lines for a relatively long period in the prefetch cache, and wherein further, upon a cache line that is stored in the long-term storage portion being hit, the cache line is promoted to said CPU from the long-term storage portion.

2. The device of claim 1 wherein the prefetch cache is configured to retrieve the sequential cache lines when the system memory bus is not being used by the processor.

3. The device of claim 2 wherein the sequential cache lines are in sequence with a plurality of cache lines previously accessed by the processor.

4. The device of claim 1 wherein the memory controller is a North bridge of the computer system.

5. The device of claim 1 wherein the cache lines are 64-byte cache lines.

6. The device of claim 1 wherein the cache lines are 128-byte cache lines.

7. A system for implementing sequential data prefetch for a processor of a computer system, comprising:

a processor;

a system memory;

a memory controller for coupling to the processor and the system memory and for interfacing the processor to the system memory via a system memory bus; and

a prefetch cache having short-term storage and having long-term storage and included in the memory controller, the prefetch cache configured to access the system memory to retrieve and store a plurality of sequential cache lines subsequent to a processor access to the system memory, wherein the memory controller is configured to track processor accesses to system memory and to interrupt a prefetch access to the system memory upon detection of a processor access to the system memory, and wherein the short-term storage portion is configured to initially store the cache lines, wherein a plurality of non-hit cache lines are transferred from the short-term storage portion to the long-term storage portion to retain the plurality of non-hit cache lines for a relatively long period in the prefetch cache, and wherein further, upon a cache line that is stored in the long-term storage portion being hit, the cache line is promoted to said CPU from the long-term storage portion.

8. The system of claim 7 wherein the prefetch cache is configured to retrieve the sequential cache lines when the system memory bus is not used by the processor.

9. The system of claim 8 wherein the sequential cache lines are in sequence with a plurality of cache lines previously accessed by the processor.

10. The system of claim 7 wherein the memory controller is a North bridge of the computer system.

11. The system of claim 7 wherein the cache lines are 64-byte cache lines.

12. The system of claim 7 wherein the cache lines are 128-byte cache lines.

13. The system of claim 7 wherein the sequential cache lines are in sequence with a plurality of cache lines previously accessed by the processor.

14. The system of claim 7 wherein the prefetch cache is at least 16 KB.

15. A method for accessing data for a computer system central processor unit, comprising:

fetching a first plurality of cache lines from a system memory and providing the cache lines to the processor;

detecting an idle time for a system memory bus coupled to the system memory indicating the system memory is not being accessed by the processor;

fetching a second plurality of cache lines from the system memory and storing the second plurality of cache lines in a prefetch cache having a short-term storage and having a long-term storage, wherein the second plurality of cache lines are in sequence with respect to the first plurality of cache lines;

upon a prefetch cache hit during a subsequent access by the processor, transferring data from the second plurality of cache lines stored in the prefetch cache to the processor;

tracking accesses to system memory by the central processor unit; and

interrupting the fetching of the second plurality of cache lines when the central processor unit requests an access to the system memory via the system memory bus;

wherein the short-term storage is configured to initially store the second plurality of cache lines, wherein a plurality of non-hit cache lines of the second plurality of cache lines are transferred from the short-term storage to the long-term storage to retain the plurality of non-hit cache lines for a relatively long period in the prefetch cache, and wherein further, upon a cache line that is stored in the long-term storage portion being hit, the cache line is promoted to said CPU fro the long-term storage.

16. The method of claim 15 wherein the first plurality of cache lines are fetched from the system memory upon a cache miss in an L2 cache of the processor.

17. The method of claim 15 wherein the memory controller is a North bridge of the computer system.

18. A method for prefetching a back sector of a cache line for a central processor unit (CPU) of a computer system, comprising:

fetching an upper sector of a cache line from a system memory and providing the cache line to the central processor unit;

detecting an idle time for a system memory bus coupled to the system memory indicating the system memory is not being accessed by the central processor unit;

fetching a lower sector of the cache line from the system memory and storing the lower sector in a prefetch cache having a short-term storage portion and a long-term storage portion;

upon a prefetch cache hit during subsequent access by the central processor unit, transferring data from the lower sector stored in the prefetch cache to an L1 cache of the central processor unit; and

tracking accesses to system memory by the central processor unit (CPU); and

interrupting the fetching of the lower sector when the central processor unit requests an access to the system memory;

wherein the short-term storage portion is configured to initially store the cache lines, wherein a plurality of non-hit cache lines are transferred from the short-term storage portion to the long-term storage portion to retain the plurality of non-hit cache lines for a relatively long period in the prefetch cache, and wherein further, upon a cache line that is stored in the long-term storage portion being hit, the cache line is promoted to said CPU from the long-term storage portion.

19. The method of claim 18 further comprising:

fetching a plurality of sequential cache lines ahead of the upper sector from a system memory and providing the sequential cache lines to the processor.

20. The method of claim 19 wherein the plurality of sequential cache lines are fetched from the system memory upon a cache miss in an L2 cache of the processor.

21. The method of claim 19 wherein the prefetch cache is larger than 2 KB.

22. The method of claim 18 wherein the method for prefetching a back sector of a cache line is implemented by a memory controller in a North bridge of the computer system.

23. The method of claim 18, wherein the cache lines are in sequence with a plurality of cache lines previously accessed by the processor.

24. The method of claim 18 wherein the L1 cache is a sectored cache.

25. The method of claim 18, further comprising:

fetching an upper sector of a cache line by the CPU from system memory; and

once an idle time is detected for the system memory bus, fetching a lower sector of the cache line is fetched from the system memory and storing the lower sector into the prefetch cache.