Error detection/correction based memory management

• US 8,683,298 B2
• Filed: 11/13/2012
• Issued: 03/25/2014
• Est. Priority Date: 10/27/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Reche, Cory J., Martin, Timothy F., Nevill, Laland R.
• Primary Examiner(s): Duncan, Marc
• Application Number:
  US13/675,870
• Publication Number:
  US 20130073898A1
• Time in Patent Office: 497 Days
• Field of Search: 714/6.13, 714/6.32, 714/47.2, 714/762, 714/773
• US Class Current: 714/773
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/2053 where persistent mass storage functionality or persistent mass storage control functionality is redundant error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Abstract

The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

Claims

1. An apparatus, comprising:

a memory device; and

a controller coupled to the memory device and configured to control;

performing a read operation on a group of memory cells;

responsive to determining that the read operation results in an uncorrectable error, determining whether to retire the group of memory cells based, at least partially, on a status of an indicator corresponding to the group of memory cells, wherein the status of the indicator indicates whether the group of memory cells has a previous uncorrectable error associated therewith; and

storing the indicator corresponding to the group of memory cells within the group of memory cells.

2. The apparatus of claim 1, wherein the group of memory cells is a block of memory cells configured to be erased together.

3. The apparatus of claim 1, wherein the group of memory cells is a page of memory cells configured to be programmed together.

4. The apparatus of claim 1, wherein the controller is configured to control updating the status of the indicator corresponding to the group of memory cells responsive to the read operation resulting in an uncorrectable error.

5. The apparatus of claim 4, wherein updating the status of the indicator comprises setting a flag.

6. The apparatus of claim 4, wherein updating the status of the indicator comprises incrementing a counter.

7. The apparatus of claim 1, wherein the controller is configured to control retiring the group of memory cells if the status of the indicator indicates that a threshold number of uncorrectable errors associated with the group of memory cells has been reached.

8. The apparatus of claim 1, wherein the controller is configured to control retiring the group of memory cells if the status of the indicator indicates the group of memory cells has a previous uncorrectable error associated therewith.

9. An apparatus, comprising:

a memory device; and

a controller coupled to the memory device and configured to control;

determining an uncorrectable error has occurred in association with a read operation performed on a group of memory cells of the memory device;

determining a status of an indicator corresponding to the group of memory cells, wherein the status of the indicator indicates whether the group of memory cells has a previous uncorrectable error associated therewith; and

tracking a ratio of total uncorrectable errors to total data throughput associated with the memory device.

10. The apparatus of claim 9, wherein the controller is configured to control determining whether to retire the group of memory cells in response to the determined status of the indicator.

11. The apparatus of claim 9, wherein the controller is configured to control updating the status of the indicator corresponding to the group of memory cells in response to a determination that an uncorrectable error has occurred in association with the read.

12. The apparatus of claim 9, wherein the controller is configured to control retiring the group of memory cells when the determined status of the indicator corresponding to the group of memory cells indicates that a threshold number of uncorrectable errors have occurred in association with read operations performed on the group of memory cells.

13. The apparatus of claim 12, wherein the threshold number is variable.

14. The apparatus of claim 13, wherein the threshold number is decreased based, at least partially, on at least one of:

an age of the memory device; and

a number of program/erase cycles performed on the group of memory cells.

15. An apparatus, comprising:

a memory device; and

a controller coupled to the memory device and configured to control;

determining whether a read operation performed on a group of memory cells results in an uncorrectable error;

determining whether the group of memory cells has experienced a threshold number of uncorrectable errors in association with a number of previous read operations;

retiring the group of memory cells if it is determined that the group of memory cells has experienced the threshold number of uncorrectable errors;

adjusting the threshold number of uncorrectable errors based, at least partially, on at least one of;

an age of the memory device; and

an amount of program/erase cycles performed on the group of memory cells.

16. The apparatus of claim 15, wherein an indicator corresponding to the group of memory cells includes a status that indicates whether the group of memory cells has experienced the threshold number of uncorrectable errors.

17. The apparatus of claim 16, wherein the indicator is stored within the group of memory cells.

18. The apparatus of claim 16, wherein the indicator is a counter.

19. The apparatus of claim 15, wherein the controller is configured to control tracking a ratio of total uncorrectable errors to total data throughput associated with the memory device.

20. The apparatus of claim 15, wherein the group of memory cells is a block of memory cells configured to be erased together.