Method and system for feed-forward advanced process control

• US 8,683,395 B2
• Filed: 04/22/2013
• Issued: 03/25/2014
• Est. Priority Date: 04/14/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chih-Jen, Lin, Chun-Hung, Lin, Juin-Hung, Chung, Hsueh-Yi, Turn, Li-Kong, Chang, Keh-Wen
• Primary Examiner(s): DOAN, NGHIA M
• Application Number:
  US13/867,890
• Publication Number:
  US 20130239073A1
• Time in Patent Office: 337 Days
• Field of Search: 716 50- 55, 430/5, 430/30
• US Class Current: 716/54
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70558 Dose control, i.e. achievement of a desired dose
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]

Abstract

Embodiments of the present disclosure disclose a method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool. The method includes selecting a previously processed wafer having a past integrated circuit design different than the new integrated circuit design, selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, and creating a field layout and associated baseline exposure dose map for the new integrated circuit design. The method also includes refining each field in the baseline exposure dose map based on a difference between an average CD for the previously processed wafer and an average CD for each field in the field layout and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer.

Claims

1. A method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool, the method comprising:

selecting a previously processed wafer having a past integrated circuit design, wherein the past integrated circuit design is different than the new integrated circuit design;

selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, the plurality of CD data points having a first average CD;

creating a field layout and associated baseline exposure dose map for the new integrated circuit design, each field in the field layout having a second average CD;

refining each field in the baseline exposure dose map based on a difference between the first average CD for the previously processed wafer and the second average CD for each field in the field layout; and

controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer.

2. The method of claim 1, further including, after selecting the plurality of CD data points, creating an inter-field model of the CD data points with a polynomial function that relates CD to position on the previously processed wafer.

3. The method of claim 2,

wherein the average CD for the previously processed wafer is calculated using the inter-field model;

and

wherein the average CD for each field in the field layout is calculated using the inter-field model.

4. The method of claim 2, wherein the polynomial function is a Zernike polynomial function.

5. The method of claim 1, wherein refining each field in the baseline exposure dose map includes:

calculating a dose adjustment for each field in the baseline exposure dose map based on the difference between the average CD for the previously processed wafer and the average CD for each field in the field layout; and

adding to each field of the baseline exposure dose map the respective dose adjustment.

6. The method of claim 5, wherein the calculating the dose adjustment for each field is further based on exposure characteristic data for the photolithography tool that represents the relationship between exposure dose and CD.

7. The method of claim 1, wherein the selecting the previously processed wafer is based on one or more of the similarity of the past integrated circuit design to the new integrated circuit design, an amount of time since the previously processed wafer was processed, and the process tools used to form the past integrated circuit design on the previously processed wafer.

8. The method of claim 1, wherein the selecting the plurality of CD data points includes:

selecting the plurality of CD data points from a plurality of fields on the previously processed wafer; and

selecting a subset of the plurality of CD data points, the subset including CD data points extracted from a plurality of fields on the previously processed wafer.

9. The method of claim 8, wherein the selecting the subset includes:

grouping fields on the processed wafer into a plurality of groups;

randomly selecting a primary field from each of the plurality of groups; and

selecting a first number of CD data points from each of the primary fields and a second number of CD data points from each of the remaining fields on the previously processed wafer, the first number being greater than the second number.

10. The method of claim 9,

wherein the plurality of groups includes four groups;

and

wherein the first number of CD data points includes approximately sixty data points and the second number of CD data points includes approximately sixteen data points.

11. An advanced process control (APC) system for forming a new integrated circuit design on a semiconductor wafer with a semiconductor processing tool, the system comprising:

a database operable to store historical data about processed wafers; and

a controller operable to control the semiconductor processing tool based on a plurality of instructions stored in a non-transitory, computer-readable memory, the plurality of instructions including instructions that;

select, from the historical data, a processed wafer having a past integrated circuit design, wherein the past integrated circuit design is different than the new integrated circuit design;

select a plurality of critical dimension (CD) data points extracted from the processed wafer after the processed wafer was etched, the plurality of CD data points having a first average CD;

create a field layout and associated baseline exposure dose map for the new integrated circuit design, each field in the field layout having a second average CD;

refine each field in the baseline exposure dose map based on a difference between the first average CD for the processed wafer and the second average CD for each field in the field layout; and

control the exposure of the semiconductor processing tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer.

12. The APC system of claim 11, wherein the plurality of instructions further include instructions that create an inter-field model of the CD data points with a polynomial function that relates CD to position on the processed wafer.

13. The APC system of claim 12,

wherein the average CD for the processed wafer is calculated using the inter-field model;

and

wherein the average CD for each field in the field layout is calculated using the inter-field model.

14. The APC system of claim 11, wherein the instructions that refine each field in the baseline exposure dose map include instructions that:

calculate a dose adjustment for each field in the baseline exposure dose map based on the difference between the average CD for the processed wafer and the average CD for each field in the field layout; and

add to each field of the baseline exposure dose map the respective dose adjustment.

15. The APC system of claim 11, wherein the instructions that select the processed wafer do so based on one or more of the similarity of the past chip design to the new chip design, an amount of time since the processed wafer was processed by the semiconductor processing tool, and an identity of semiconductor processing tools used to process the processed wafer.

16. The APC system of claim 11, wherein the instructions that select the plurality of CD data points include instructions that:

select the plurality of CD data points from a plurality of fields on the processed wafer; and

select a subset of the plurality of CD data points, the subset including CD data points extracted from a plurality of fields on the processed wafer.

17. The APC system of claim 16, wherein the instructions that select a subset of data points include instructions that:

group fields on the processed wafer into a plurality of groups;

randomly select a primary field from each of the plurality of groups; and

select a first amount of data points from each of the primary fields and a second amount of data points from each of the remaining fields on the wafer, the first amount being greater than the second amount.

18. A method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool, the method comprising:

selecting a previously processed wafer having a past integrated circuit design, the past integrated circuit design being different than the new integrated circuit design, and the previously processed wafer having a plurality of critical dimension (CD) data points extracted therefrom after being etched, the plurality of CD data points having a first average CD;

selecting a subset of the plurality of critical dimension (CD) data points by grouping fields on the processed wafer into a plurality of groups and selecting CD data points from a plurality of fields in each of the plurality of groups;

creating an initial exposure dose map for the new integrated circuit design using the subset of the plurality of CD data points, wherein creating the initial exposure dose map includes;

creating a field layout and associated baseline exposure dose map for the new integrated circuit design, each field in the field layout having a second average CD; and

refining each field in the baseline exposure dose map based on a difference between the first average CD for the previously processed wafer and the second average CD for each field in the field layout; and

controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new integrated circuit design on the semiconductor wafer.

19. The method of claim 18, wherein selecting CD data points from the plurality of fields in each of the plurality of groups includes:

randomly selecting a primary field from each of the plurality of groups; and

selecting a first number of CD data points from each of the primary fields and a second number of CD data points from each of the remaining fields on the wafer, the first number being greater than the second number.