Hierarchical design flow generator
First Claim
1. A hierarchical design flow generator, comprising:
- a partitioner configured to partition, employing a processor, a hierarchical design flow for an integrated circuit design into a late design flow portion and an early design flow portion;
a timing budgeter configured to provide a timing budget for said integrated circuit design based on initial timing constraints and progressive time constraints generated from said late design flow portion and said early design flow portion; and
a modeler configured to develop a model for a top level implementation of said integrated circuit design based on said timing budget and block implementations generated during said late design flow portion.
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Abstract
A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow portion and the early design flow portion and (3) a modeler configured to develop a model for a top level implementation of the IC design based on the timing budget and block implementations generated during the late design flow portion.
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Citations
20 Claims
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1. A hierarchical design flow generator, comprising:
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a partitioner configured to partition, employing a processor, a hierarchical design flow for an integrated circuit design into a late design flow portion and an early design flow portion; a timing budgeter configured to provide a timing budget for said integrated circuit design based on initial timing constraints and progressive time constraints generated from said late design flow portion and said early design flow portion; and a modeler configured to develop a model for a top level implementation of said integrated circuit design based on said timing budget and block implementations generated during said late design flow portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification