Hierarchical design flow generator

• US 8,683,407 B2
• Filed: 08/20/2013
• Issued: 03/25/2014
• Est. Priority Date: 07/27/2009
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Rao, Vishwas M., Parker, James C.
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/971,560
• Publication Number:
  US 20130339912A1
• Time in Patent Office: 217 Days
• Field of Search: 716/110, 716/113, 716/122, 716124-125
• US Class Current: 716/110
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow portion and the early design flow portion and (3) a modeler configured to develop a model for a top level implementation of the IC design based on the timing budget and block implementations generated during the late design flow portion.

Claims

1. A hierarchical design flow generator, comprising:

a partitioner configured to partition, employing a processor, a hierarchical design flow for an integrated circuit design into a late design flow portion and an early design flow portion;

a timing budgeter configured to provide a timing budget for said integrated circuit design based on initial timing constraints and progressive time constraints generated from said late design flow portion and said early design flow portion; and

a modeler configured to develop a model for a top level implementation of said integrated circuit design based on said timing budget and block implementations generated during said late design flow portion.

2. The hierarchical design flow generator as recited in claim 1 wherein said partitioner, said timing budgeter and said modeler are further configured to interact with at least one EDA tool to perform its designated function.

3. The hierarchical design flow generator as recited in claim 1 wherein said timing budgeter is configured to perform re-negotiations of said timing budget and update said timing budget based thereon.

4. The hierarchical design flow generator as recited in claim 3 wherein said re-negotiations are based on iterative implementations of said timing budget.

5. The hierarchical design flow generator as recited in claim 1 wherein said timing budgeter is configured to receive timing budget information for logic that is not presently being used in a block of said integrated circuit design.

6. The hierarchical design flow generator as recited in claim 1 wherein said modeler is configured to iteratively develop said top level model.

7. The hierarchical design flow generator as recited in claim 1 wherein said late design flow portion is substantially the same for different design flow methodologies.

8. The hierarchical design flow generator as recited in claim 1 wherein said timing budgeter is configured to establish, for said early design flow portion, an early timing budget based on achievable input and output constraints from a bottom-up block-flow of said early design flow portion.

9. The hierarchical design flow generator as recited in claim 8 wherein said modeler is configured to employ said early timing budget to generate an early top-level implementation and an early block level implementation of said integrated circuit design.

10. The hierarchical design flow generator as recited in claim 9 wherein said modeler is configured to generate a final block level implementation based on said early block level implementation.

11. The hierarchical design flow generator as recited in claim 10 wherein said timing budgeter is configured to establish a final timing budget based on said early top-level implementation and said final block level implementation.

12. The hierarchical design flow generator as recited in claim 11 wherein said modeler is configured to provide said top level implementation based on said final timing budget and said final block level implementation.

13. The hierarchical design flow generator as recited in claim 10 wherein said timing budgeter is configured to establish a final timing budget based on said early top-level implementation and timing interface violations from said final block level implementation.

14. The hierarchical design flow generator as recited in claim 1 wherein said early design flow portion includes a functional block implementation section having a top-down block-flow and a bottom-up block-flow.

15. The hierarchical design flow generator as recited in claim 14 wherein said early design flow portion includes a parallel top-level design flow.

16. The hierarchical design flow generator as recited in claim 15 wherein said timing budgeter is further configured to generate an early timing budget to be employed by said top-down block-flow and said parallel top-level design flow.

17. The hierarchical design flow generator as recited in claim 1 wherein said late design flow portion and said early design flow portion allow simultaneous top-down and bottom-up design methodologies for said integrated circuit design.

18. The hierarchical design flow generator as recited in claim 1 wherein said timing budgeter is configured to receive said initial timing constraints.

19. The hierarchical design flow generator as recited in claim 1 wherein said top level implementation of said integrated circuit design is a final top level implementation.

20. The hierarchical design flow generator as recited in claim 1 wherein said partitioner is configured to partition all of said hierarchical design flow into said late design flow portion and said early design flow portion.