Operational cycle assignment in a configurable IC

• US 8,683,410 B2
• Filed: 12/10/2010
• Issued: 03/25/2014
• Est. Priority Date: 12/01/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Rohe, Andre, Teig, Steven
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US12/965,815
• Publication Number:
  US 20110145776A1
• Time in Patent Office: 1,201 Days
• Field of Search: 716/113, 716/117, 716/128, 716/129, 716/116, 713/1, 713/100, 713/501, 713/600
• US Class Current: 716/116
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.

Claims

1. A method for mapping an integrated circuit (“

IC”

) design to an IC, the design comprising a plurality of components, the method comprising;

identifying a plurality of multi-path components that are each on multiple signal paths;

for each component, computing, by a computer, a normalized metric value that falls within a fixed numerical range to express a position of the component on a uniform scale that is used to express positions of all components with respect to each other,

said computing comprising computing, for each multi-path component of a subset of the plurality of multi-path components, the normalized metric value based at least partially on a distance of the multi-path component to a start of a first signal path and a distance of the multi-path component to an end of a second signal path that is different from an end of the first signal path; and

based on the normalized metric value, assigning the component to one of a plurality of operational cycles.

2. The method of claim 1, wherein assigning the component to an operational cycle comprises:

identifying a configurable circuit in the IC for configurably implementing an operation performed by the component; and

defining a configuration data set for the identified configurable circuit to implement the operation performed by the component during the operational cycle.

3. The method of claim 2, wherein the configurable circuit is a reconfigurable circuit.

4. The method of claim 1, wherein computing the normalized metric value for the multi-path component comprises:

identifying a longest signal path that includes the multi-path component; and

assigning the normalized metric value to the multi-path component based on a position of the multi-path component on the identified longest signal path.

5. The method of claim 4, wherein the normalized metric value is a value between zero and one.

6. The method of claim 4, wherein the position of the multi-path component on the identified longest signal path is measured at least partially in terms of a number of intervening components along a signal path.

7. The method of claim 4, wherein the position of the multi-path component on the identified longest signal path is measured at least partially in terms of an overall signal delay through intervening components along a signal path.

8. The method of claim 1, wherein components with higher normalized metric values are placed in later operational cycles.

9. A non-transitory computer readable medium storing a computer program which, when executed by at least one processor, designs an integrated circuit (“

IC”

) with a plurality of configurable circuits, the computer program comprising sets of instructions for;

receiving a design comprising a plurality of signal paths, each signal path defined by a set of components that are communicatively coupled; and

assigning, for each of a plurality of components, a component in a signal path to an operational cycle based at least partially on a metric value that is normalized over (i) a first distance value that expresses a signal delay between a source point of the signal path and the component, and (ii) a second distance value that expresses a signal delay between the component and a target point of the signal path, said normalized metric value falls within a fixed numerical range to express a position of the component on a uniform scale that is used to express relative positions of all components within the signal path.

10. The non-transitory computer readable medium of claim 9, wherein the component is in only one signal path, wherein the normalized metric value is defined as the first distance value divided by a sum of the first and second distance values.

11. The non-transitory computer readable medium of claim 10, wherein components with higher normalized metric values are placed in later operational cycles.

12. The non-transitory computer readable medium of claim 9, wherein the first distance value accounts for a first number of intervening components between the source point of the signal path and the component and the second distance value accounts for a second number of intervening components between the component and the target point of the signal path.

13. The non-transitory computer readable medium of claim 9, wherein the first and second distance values are normalized topological metric values.

14. The non-transitory computer readable medium of claim 9, wherein the plurality of configurable circuits are reconfigurable circuits.

15. The non-transitory computer readable medium of claim 9, wherein the operational cycle is a sub cycle of a user defined clock cycle.

16. The non-transitory computer readable medium of claim 9, wherein the set of instructions for assigning comprises a set of instructions for assigning an approximately equal number of components to each of a set of operational cycles.

17. A method for mapping an integrated circuit (“

IC”

) design to an IC, the design comprising a plurality of components, each component in one or more signal paths, the method comprising;

for each particular component of the plurality of components, calculating, by a computer, a normalized metric value based at least partially on (i) a number of components along a signal path that includes the particular component and (ii) a number of components from the start of the signal path to the particular component, wherein the normalized metric value falls within a fixed numerical range to express a position of the component on a uniform scale that is used to express positions of all components with respect to each other; and

assigning the plurality of components to different operational cycles based at least partially on the normalized metric values calculated for the plurality of components, wherein each of the different operational cycles corresponds to a unique range of normalized metric values.

18. The method of claim 17, wherein components with higher normalized metric values are placed in later operational cycles.

19. The method of claim 17, wherein the IC is a sub-cycle reconfigurable IC and the different operational cycles are sub-cycles of a user defined clock.

20. The method of claim 17, wherein assigning the plurality of components to different operational cycles comprises:

sorting the plurality of components based on the normalized metric values of the plurality of components; and

assigning an approximately equal number of components to each operational cycle.

21. The method of claim 17, wherein the normalized metric value for each particular component of the plurality of components is based at least partially on a signal path with a maximum number of components among all paths that include the particular component.

22. The method of claim 17, wherein the normalized metric value for the particular component is further based at least partially on a signal delay through components along the signal path that includes the particular component.