Test partitioning for a non-volatile memory

• US 8,683,456 B2
• Filed: 07/13/2009
• Issued: 03/25/2014
• Est. Priority Date: 07/13/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Byom, Matthew, Wakrat, Nir J., Herman, Kenneth
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): BORROMEO, JUANITO C
• Application Number:
  US12/502,128
• Publication Number:
  US 20110010698A1
• Time in Patent Office: 1,716 Days
• Field of Search: None
• US Class Current: 717/168
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2029/1206 Location of test circuitry on chip or wafer
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Abstract

Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to run a test of the memory locations in the test region. The results of the test may be stored in the general purpose region. At the completion of the test, the test results may be provided from the general purpose region and displayed to a user. The virtual partitions may be removed prior to shipping the electronic device for distribution.

Claims

1. A method of testing a non-volatile memory, the method comprising:

virtually partitioning the non-volatile memory into first and second regions;

storing a test application in the first region of the non-volatile memory;

executing the test application to run a test of the second region of the non-volatile memory;

wherein the executing the test application comprises;

(a) erasing a block of the second region;

(b) programming a test pattern to a page of the second region in the erased block;

(c) performing a read operation on the page; and

(d) determining whether the read operation produces the test pattern;

and

removing the virtual partitioning.

2. The method of claim 1, further comprising storing results of the test in the first region of the non-volatile memory.

3. The method of claim 1, wherein the non-volatile memory is of an electronic device, the method further comprising evaluating the results using the electronic device.

4. The method of claim 1, further comprising displaying the results of the test to a user.

5. The method of claim 4, wherein the displaying occurs during the executing, after the executing, or both during and after the executing.

6. The method of claim 1, wherein the virtually partitioning comprises:

giving control of physical addresses corresponding to the first region to a first software module; and

giving control of physical addresses corresponding to the second region to a second software module.

7. A method of testing a non-volatile memory, the method comprising:

virtually partitioning the non-volatile memory into first and second regions;

storing a test application in the first region of the non-volatile memory; and

executing the test application to run a test of the second region of the non-volatile memory, wherein the executing the test application comprises;

(a) erasing a block of the second region;

(b) programming a test pattern to a page of the second region in the erased block;

(c) performing a read operation on the page; and

(d) determining whether the read operation produces the test pattern.

8. The method of claim 7, further comprising:

(e) repeating steps (a)-(d) for a plurality of portions in the second region.

9. A method of preparing an electronic device for shipment, the electronic device comprising a non-volatile memory, the method comprising:

creating first and second virtual partitions of the non-volatile memory;

testing the second virtual partition;

storing results of the testing in the first virtual partition; and

removing the virtual partitions before shipment of the electronic device,

wherein said testing the second virtual partition comprises;

(a) erasing a block of the second region;

(b) programming a test pattern to a page of the second region in the erased block;

(c) performing a read operation on the page; and

(d) determining whether the read operation produces the test pattern.

10. The method of claim 9, further comprising determining whether the results of the testing meet a predetermined specification, wherein the removing is performed responsive to the determining.

11. The method of claim 10, wherein the determining is performed by the electronic device.

12. The method of claim 9, wherein the creating comprises performing at least one of a firmware update of the electronic device and a software update of the electronic device.

13. The method of claim 9, wherein the testing comprises identifying memory locations in the second virtual partition that contain defects.

14. The method of claim 9, wherein the testing comprises executing a test application stored in the first virtual partition.

15. The method of claim 14, further comprising loading the non-volatile memory with a shipping application after the removing.

16. The method of claim 9, wherein the storing occurs during the testing.

17. An electronic device comprising:

a non-volatile memory; and

a system-on-a-chip comprising control circuitry configured to operate under the control of a plurality of modules, the modules comprising;

a test application;

a translation layer for controlling access by the test application to a first portion of the non-volatile memory; and

an access layer for controlling access by the test application to a second portion of the non-volatile memory,

wherein the test application is configured to test the second region of the non-volatile memory using the access layer by;

(a) erasing a block of the second region;

(b) programming a test pattern to a page of the second region in the erased block;

(c) performing a read operation on the page; and

(d) determining whether the read operation produces the test pattern.

18. The electronic device of claim 17, wherein the translation layer and the access layer are software modules.

19. The electronic device of claim 17, wherein the non-volatile memory comprises a flash memory and the translation layer comprises a flash translation layer.

20. The electronic device of claim 17, wherein the plurality of modules further comprise a file system for interfacing the test application with the translation layer.

21. The electronic device of claim 20, wherein the file system is configured to provide logical addresses to the translation layer, and wherein the translation layer is configured to convert the logical addresses to physical addresses corresponding to memory locations in the first portion of the non-volatile memory.

22. The electronic device of claim 17, wherein the modules further comprise a software/hardware interface for communicating with the non-volatile memory, wherein the software/hardware interface is configured to access the non-volatile memory responsive to commands from the translation layer and the access layer.

23. The electronic device of claim 17, wherein the test application is configured to:

receive test results for the second region of the non-volatile memory from the access layer; and

store the test results in the first region of the non-volatile memory using the translation layer.