Method for manufacturing a CMOS device having dual metal gate
First Claim
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1. A method for manufacturing a complementary metal oxide semiconductor (CMOS) device having dual metal gate comprising steps of:
- providing a substrate having a first active region and a second active region defined thereon;
forming a first conductive type transistor having a first gate and a second conductive type transistor having a second gate respectively in the first active region and the second active region;
performing a salicide process to transform a top part of the second gate into a salicide layer while leave a bottom part of the second gate without change;
forming an inter-level dielectric (ILD) layer exposing tops of the first conductive type transistor and the second conductive type transistor on the substrate after the salicide process;
performing a first etching process to remove a portion of the first gate of the first conductive type transistor to form an opening in the first active region, and a high-K gate dielectric layer of the first conductive type transistor being exposed in a bottom of the opening; and
forming at least a first metal layer in the opening.
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Abstract
A method for manufacturing a CMOS device includes providing a substrate having a first active region and a second active region defined thereon, forming a first conductive type transistor and a second conductive type transistor respectively in the first and the second active regions, performing a salicide process, forming an ILD layer, performing a first etching process to remove a first gate of the first conductive type transistor and to form an opening while a high-K gate dielectric layer is exposed in a bottom of the opening, and forming at least a first metal layer in the opening.
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Citations
12 Claims
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1. A method for manufacturing a complementary metal oxide semiconductor (CMOS) device having dual metal gate comprising steps of:
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providing a substrate having a first active region and a second active region defined thereon; forming a first conductive type transistor having a first gate and a second conductive type transistor having a second gate respectively in the first active region and the second active region; performing a salicide process to transform a top part of the second gate into a salicide layer while leave a bottom part of the second gate without change; forming an inter-level dielectric (ILD) layer exposing tops of the first conductive type transistor and the second conductive type transistor on the substrate after the salicide process; performing a first etching process to remove a portion of the first gate of the first conductive type transistor to form an opening in the first active region, and a high-K gate dielectric layer of the first conductive type transistor being exposed in a bottom of the opening; and forming at least a first metal layer in the opening. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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