Self-aligned semiconductor trench structures

• US 8,685,859 B2
• Filed: 09/26/2013
• Issued: 04/01/2014
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lane, Richard, Werner, Juengling
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US14/038,365
• Publication Number:
  US 20140030869A1
• Time in Patent Office: 187 Days
• Field of Search: 438/424, 438/437, 438/696, 257/510, 257/E21.243
• US Class Current: 438/696
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.

Claims

1. A method of forming a device, comprising:

providing a substrate;

forming a plurality of first trenches in a substrate, comprising;

forming a plurality of placeholder lines extending in a first direction; and

etching the first trenches through a surface exposed between the placeholder lines;

filling the first trenches with an isolation material;

forming a plurality of second trenches in the substrate, comprising;

selectively removing the placeholder lines to form isolation lines comprising the isolation material, the isolation lines extending in the first direction and protruding above the surface;

forming sidewall spacers on sidewalls of the isolation lines; and

etching the second trenches through the surface exposed between the sidewall spacers of adjacent isolation lines.

2. The method of claim 1, wherein forming the placeholder lines comprises depositing a layer of placeholder material and lithographically patterning.

3. The method of claim 2, wherein the layer of placeholder material comprises polysilicon.

4. The method of claim 2, wherein forming the placeholder lines further comprises depositing a hardmask material on the placeholder material and lithographically patterning to form hardmask lines over the placeholder material.

5. The method of claim 2, further comprising chemical-mechanically polishing after filling the first trenches to form a substantially planar surface, wherein the substantially planar surface comprises alternating placeholder lines and isolation lines.

6. The method of claim 2, further comprising providing an etch stop material interposed between the substrate and the placeholder material.

7. The method of claim 6, wherein the first trenches extend below the surface at a first trench depth and the second trenches extend below the surface at a second depth shallower than the first depth.

8. The method of claim 1, wherein forming the first trenches further comprises conformally depositing an initial sidewall spacer material over the placeholder lines and directionally etching the initial sidewall spacer material such that the initial sidewall spacer material remains over sidewalls of the placeholder lines.

9. The method of claim 8, wherein forming the placeholder lines further comprises forming lines of hardmask material over the placeholder material, and wherein the initial sidewall spacer material and hardmask material comprise the same material.

10. The method of claim 1, wherein filling the first trenches comprises lining the first trenches with a first liner after etching the first trenches.

11. The method of claim 10, further comprising lining the second trenches with a second liner comprising a second liner material after etching the second trenches, wherein the first liner comprises a first liner material different from the second liner material.

12. A method of forming a device, comprising:

forming a plurality of placeholder lines on an etch stop layer;

etching a first set of trenches through the etch stop layer exposed between the placeholder lines;

filling the first set of trenches between the placeholder lines with an isolation material;

selectively removing the placeholder lines to form isolation lines comprising the isolation material;

forming pairs of sidewall spacers on sidewalls of the isolation lines; and

etching a second set of trenches through the etch stop layer exposed between the isolation lines.

13. The method of claim 12, wherein the etch stop layer comprises silicon nitride.

14. The method of claim 12, wherein the etch stop layer comprises aluminum oxide.

15. The method of claim 12, wherein forming the sidewall spacers comprises:

conformally depositing a sidewall spacer material over the isolation lines; and

directionally etching the sidewall spacer material, such that the sidewall spacer material remains over sidewalls of the isolation lines while the sidewall spacer material is removed between the isolation lines.

16. The method of claim 12,

wherein filling the first set of trenches comprises lining the first set of trenches with a first liner comprising a plurality of layers after etching the first trenches;

and

further comprising lining the second set of trenches with a second liner after etching the second trenches.

17. The method of claim 16, wherein the second liner comprises an oxide layer.

18. The method of claim 17, wherein the first liner comprise a barrier layer.

19. The method of claim 18, wherein the barrier layer comprises silicon nitride.

20. The method of claim 16, wherein the first liner comprises a silicon oxide layer and a silicon nitride layer.