Integrated circuit semiconductor devices including channel trenches and related methods of manufacturing

• US 8,686,393 B2
• Filed: 01/13/2012
• Issued: 04/01/2014
• Est. Priority Date: 03/29/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yu, Jihyung, Ha, Daewon, Kim, Song yi
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): BACHNER, ROBERT G
• Application Number:
  US13/349,714
• Publication Number:
  US 20120248400A1
• Time in Patent Office: 809 Days
• Field of Search: 257/E47.001, 257/75, 257/5, 365/49.1
• US Class Current: 257/5
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

An integrated circuit device may include a semiconductor substrate including an active region and a transistor in the active region. The transistor may include first and second spaced apart source/drain regions in the active region of the semiconductor substrate, and a semiconductor channel region between the first and second source/drain regions. The semiconductor channel region may include a plurality of channel trenches therein between the first and second source/drain regions. A gate insulating layer may be provided on the channel region including sidewalls of the plurality of channel trenches, and a gate electrode may be provided on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches. Related methods are also discussed.

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate including cell array regions and a core region between the cell array regions;

a plurality of phase-change memory cells in each of the cell array regions; and

cell driving transistors in the core region configured to drive the phase-change memory cells, wherein each of the cell driving transistors comprises,

first and second spaced apart source/drain regions in the semiconductor substrate,

a semiconductor channel region between the first and second source/drain regions, wherein the semiconductor channel region includes a plurality of channel trenches therein,

a gate insulating layer on the semiconductor channel region including the plurality of channel trenches, and

a gate electrode on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches.

2. The semiconductor memory device of claim 1, further comprising:

a device isolation layer on portions of the semiconductor substrate in the core region wherein the device isolation layer defines a plurality of active regions, wherein each of the active regions includes a respective one of the cell driving transistors,

wherein each of the active regions has a rectangular shape having an active region length and an active region width less than the active region length in a plane of a surface of the semiconductor substrate, wherein each of the channel trenches has a rectangular shape having a trench length and a trench width less than the trench length in the plane, and wherein the active region length is substantially parallel with the trench length of the channel trenches therein.

3. The semiconductor memory device of claim 2, wherein a depth of a bottom surface of the device isolation layer into the semiconductor substrate is substantially the same as a depth of a bottom surface of each of the channel trenches into the semiconductor substrate.

4. The semiconductor memory device of claim 2, wherein the trench width of each of the channel trenches is in a range of about ½

to about 1/140 of the active region width.

5. The semiconductor memory device of claim 2, wherein the gate electrode of one of the cell driving transistors crosses continuously over the channel trenches of the respective semiconductor channel region, and wherein the trench length of the channel trenches of the respective semiconductor channel region is less than a width of the gate electrode of the cell driving transistor in a direction of the trench length.

6. The semiconductor memory device of claim 1, further comprising:

a device isolation layer in the semiconductor substrate to define a first active region in the cell array region and a second active region in the core region,

wherein a depth of a bottom surface of the device isolation layer from a surface of the semiconductor substrate is substantially the same as a depth of a bottom surface of each of the channel trenches from the surface of the semiconductor substrate.

7. The semiconductor memory device of claim 1, wherein the semiconductor substrate further comprises a peripheral circuit region around the cell array and core regions, wherein the peripheral circuit region includes peripheral circuits therein, and wherein the portions of the semiconductor substrate in the cell array and peripheral circuit regions have a substantially planar active surface.

8. The semiconductor memory device of claim 7, wherein one of the peripheral circuits comprises:

a peripheral gate electrode on the active surface of the semiconductor substrate in the peripheral circuit region;

peripheral source/drain regions on opposite sides of the peripheral gate electrode; and

a peripheral gate insulating layer between the peripheral gate electrode and the semiconductor substrate.

9. The semiconductor memory device of claim 1 further comprising:

a word line in the cell array region; and

a bit line crossing the word line in the cell array region;

wherein one of the phase change memory cells comprises a diode and a phase-change pattern electrically coupled in series between the word line and the bit line.

10. The semiconductor memory device of claim 9, wherein the word line and the bit line are electrically connected to respective ones of the cell driving transistors.