Oxide semiconductor device formed by using multi-tone mask

• US 8,686,417 B2
• Filed: 07/23/2012
• Issued: 04/01/2014
• Est. Priority Date: 10/24/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Suzawa, Hideomi, Sasagawa, Shinya, Muraoka, Taiga, Ito, Shunichi, Hosoba, Miyuki
• Primary Examiner(s): Malsawma, Lex
• Assistant Examiner(s): ZHU, SHENG-BAI
• Application Number:
  US13/555,579
• Publication Number:
  US 20120286266A1
• Time in Patent Office: 617 Days
• Field of Search: 257/43, 257/72, 257/288, 257/347, 257/368, 257/E21.414, 438/104, 438/151, 438/148, 438/796
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.

Claims

1. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium;

a source electrode layer over the oxide semiconductor layer; and

a drain electrode layer over the oxide semiconductor layer,

wherein an upper surface of the oxide semiconductor layer between the source electrode layer and the drain electrode layer is etched so that a portion of the oxide semiconductor layer is thinner than portions of the oxide semiconductor layer below the source electrode layer and the drain electrode layer,

wherein edge portions of the oxide semiconductor layer are step-like and comprise first edges and second edges,

wherein the first edges of the oxide semiconductor layer are aligned with outer side edges of the source electrode layer and the drain electrode layer,

wherein the second edges of the oxide semiconductor layer extend beyond the outer side edges of the source electrode layer and the drain electrode layer,

wherein the second edges of the oxide semiconductor layer have curved surfaces,

wherein the gate electrode layer comprises a stack of a first layer comprising Ti and a second layer comprising Cu,

wherein the gate insulating layer comprises a stack of a silicon nitride layer and a first silicon oxide layer, and

wherein the silicon nitride layer covers the second layer.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer further includes gallium, and zinc.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is in direct contact with the source electrode layer and the drain electrode layer.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has an amorphous structure.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a crystal grain with a grain diameter greater than or equal to 1 nm and less than or equal to 10 nm.

6. The semiconductor device according to claim 1,

wherein the first layer comprising Ti is stacked over the second layer comprising Cu.

7. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium;

a source electrode layer over the oxide semiconductor layer; and

a drain electrode layer over the oxide semiconductor layer,

an insulating layer over the oxide semiconductor layer, the source electrode layer and the drain electrode layer,

wherein an upper surface of the oxide semiconductor layer between the source electrode layer and the drain electrode layer is etched so that a portion of the oxide semiconductor layer is thinner than portions of the oxide semiconductor layer below the source electrode layer and the drain electrode layer,

wherein edge portions of the oxide semiconductor layer are step-like and comprise first edges and second edges,

wherein the first edges of the oxide semiconductor layer are aligned with outer side edges of the source electrode layer and the drain electrode layer,

wherein the second edges of the oxide semiconductor layer extend beyond the outer side edges of the source electrode layer and the drain electrode layer,

wherein the second edges of the oxide semiconductor layer have curved surfaces,

wherein the insulating layer is in direct contact with the gate insulating layer,

wherein the gate electrode layer comprises a stack of a first layer comprising Ti and a second layer comprising Cu,

wherein the gate insulating layer comprises a stack of a silicon nitride layer and a first silicon oxide layer, and

wherein the silicon nitride layer covers the second layer.

8. The semiconductor device according to claim 7, wherein the oxide semiconductor layer further includes gallium, and zinc.

9. The semiconductor device according to claim 7, wherein the oxide semiconductor layer is in direct contact with the source electrode layer and the drain electrode layer.

10. The semiconductor device according to claim 7, wherein the oxide semiconductor layer has an amorphous structure.

11. The semiconductor device according to claim 7,

wherein the first layer comprising Ti is stacked over the second layer comprising Cu.

12. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium;

a source electrode layer over the oxide semiconductor layer; and

a drain electrode layer over the oxide semiconductor layer,

an insulating layer over the oxide semiconductor layer, the source electrode layer and the drain electrode layer;

a planarizing insulating layer over the insulating layer,

wherein an upper surface of the oxide semiconductor layer between the source electrode layer and the drain electrode layer is etched so that a portion of the oxide semiconductor layer is thinner than portions of the oxide semiconductor layer below the source electrode layer and the drain electrode layer,

wherein edge portions of the oxide semiconductor layer are step-like and comprise first edges and second edges,

wherein the first edges of the oxide semiconductor layer are aligned with outer side edges of the source electrode layer and the drain electrode layer,

wherein the second edges of the oxide semiconductor layer extend beyond the outer side edges of the source electrode layer and the drain electrode layer,

wherein the second edges of the oxide semiconductor layer have curved surfaces,

wherein the gate electrode layer comprises a stack of a first layer comprising Ti and a second layer comprising Cu,

wherein the gate insulating layer comprises a stack of a silicon nitride layer and a first silicon oxide layer, and

wherein the silicon nitride layer covers the second layer.

13. The semiconductor device according to claim 12, wherein the oxide semiconductor layer further includes gallium, and zinc.

14. The semiconductor device according to claim 12, wherein the oxide semiconductor layer is in direct contact with the source electrode layer and the drain electrode layer.

15. The semiconductor device according to claim 12, wherein the oxide semiconductor layer has an amorphous structure.

16. The semiconductor device according to claim 12,

wherein the first layer comprising Ti is stacked over the second layer comprising Cu.

17. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium;

a source electrode layer over the oxide semiconductor layer; and

a drain electrode layer over the oxide semiconductor layer,

a silicon oxide film over the source electrode layer and the drain electrode layer,

a silicon nitride film over the silicon oxide film,

a resin layer over the silicon nitride film,

a pixel electrode layer over the resin layer,

wherein an upper surface of the oxide semiconductor layer between the source electrode layer and the drain electrode layer is etched so that a portion of the oxide semiconductor layer is thinner than portions of the oxide semiconductor layer below the source electrode layer and the drain electrode layer,

wherein edge portions of the oxide semiconductor layer are step-like and comprise first edges and second edges,

wherein the first edges of the oxide semiconductor layer are aligned with outer side edges of the source electrode layer and the drain electrode layer,

wherein the second edges of the oxide semiconductor layer extend beyond the outer side edges of the source electrode layer and the drain electrode layer,

wherein the second edges of the oxide semiconductor layer have curved surfaces,

wherein the gate electrode layer comprises a stack of a first layer comprising Ti and a second layer comprising Cu,

wherein the gate insulating layer comprises a stack of a silicon nitride layer and a first silicon oxide layer, and

wherein the silicon nitride layer covers the second layer.

18. The semiconductor device according to claim 17, wherein the oxide semiconductor layer further includes gallium, and zinc.

19. The semiconductor device according to claim 17, wherein the oxide semiconductor layer is in direct contact with the source electrode layer and the drain electrode layer.

20. The semiconductor device according to claim 17, wherein the oxide semiconductor layer has an amorphous structure.

21. A liquid crystal display device comprising the semiconductor device according to claim 17.

22. An electroluminescent display device comprising the semiconductor device according to claim 17.

23. The semiconductor device according to claim 17, wherein the resin layer comprises at least one selected from the group consisting of polyimide, acrylic, benzocyclobutene, polyamide, and epoxy.

24. The semiconductor device according to claim 17,

wherein the first layer comprising Ti is stacked over the second layer comprising Cu.