Thin film transistor having plural semiconductive oxides, thin film transistor array panel and display device including the same, and manufacturing method of thin film transistor

• US 8,686,426 B2
• Filed: 07/23/2012
• Issued: 04/01/2014
• Est. Priority Date: 04/02/2012
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Kobe Steel Limited, Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Ahn, Byung Du, Lim, Ji Hun, Kim, Gun Hee, Lee, Kyoung Won, Lee, Je Hun
• Primary Examiner(s): Tran, Tan N
• Application Number:
  US13/555,889
• Publication Number:
  US 20130256653A1
• Time in Patent Office: 617 Days
• Field of Search: 257/59, 257/72, 257/258
• US Class Current: 257/72
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A plural semiconductive oxides TFT (sos-TFT) provides improved electrical functionality in terms of charge-carrier mobility and/or threshold voltage variability. The sos-TFT may be used to form a thin film transistor array panel for display devices. An example sos-TFT includes: an insulated gate electrode; a first semiconductive oxide layer having a composition including a first semiconductive oxide; and a second semiconductive oxide layer having a different composition that also includes a semiconductive oxide. The first and second semiconductive oxide layers have respective channel regions that are capacitively influenced by a control voltage applied to the gate electrode. In one embodiment, the second semiconductive oxide layer includes at least one additional element that is not included in the first semiconductive oxide layer where the additional element is one of gallium (Ga), silicon (Si), niobium (Nb), hafnium (Hf), and germanium (Ge).

Claims

1. A semiconductive device comprising:

a gate electrode;

a gate insulating layer;

a first semiconductive oxide layer comprising a first composition that includes a first semiconductive oxide;

a second semiconductive oxide layer comprising a second composition that is different from the first composition and includes the first or a different second semiconductive oxide and that further includes at least one additional component that is not included in the first composition,

where the first and second semiconductive oxide layers overlap with one another in a common overlapping region of both, where the gate electrode insulatively overlaps at least the common overlapping region, where the gate insulating layer is interposed between the gate electrode and the common overlapping region of the first and second semiconductive oxide layers;

a source electrode connected to at least one of the first and second semiconductive oxide layers; and

a drain electrode connected to the at least one of the first and second semiconductive oxide layers, the drain electrode being spaced apart from the source electrode,

wherein the at least one additional component of the second composition includes at least one of gallium (Ga), silicon (Si), niobium (Nb), hafnium (Hf), and germanium (Ge),

wherein the first semiconductive oxide layer is interposed between the gate insulating layer and the second semiconductive oxide layer, and

a content of the additional component is in a range from about 1 at. % to about 30 at. % relative to the 100 atomic percent of the second composition.

2. The semiconductive device of claim 1, wherein the first semiconductive oxide is an indium(In)-zinc(Zn)-tin (Sn) oxide (IZTO), and the second semiconductive oxide is a zinc(Zn)-tin(Sn) oxide (ZTO).

3. The semiconductive device of claim 2, wherein

a difference between a respective content of tin (Sn) in the second composition and a respective content of tin (Sn) in the first composition is equal to or less than about 15 at. %.

4. The semiconductive device of claim 3, wherein

a respective thickness of each of the first second semiconductive oxide layers is respectively in a range from about 5 Å

to about 600 Å

.

5. The semiconductive device of claim 4, wherein

the second semiconductive oxide further includes indium (In).

6. The semiconductive device of claim 5, wherein

each of the source electrode and the drain electrode includes a layer of copper, and

each of the source electrode and the drain electrode directly contacts the second semiconductive oxide layer.

7. The semiconductive device of claim 1, wherein

the respective first and second compositions of the first and second semiconductive oxide layers are simultaneously etchable by a same predetermined etchant, and

a difference between etch rates of the first and second compositions when being etched by the predetermined etchant is equal to or less than about 100 Å

/s (Angstroms per second).

8. The semiconductive device of claim 1, wherein

the first composition includes an indium(In)-zinc(Zn)-tin(Sn) oxide (IZTO), and

the second composition includes a zinc (Zn)-tin(Sn) oxide (ZTO).

9. The semiconductive device of claim 8, wherein

the respective first and second compositions of the first and second semiconductive oxide layers are simultaneously etchable by a same predetermined etchant, and

a difference between etch rates of the first and second compositions when being etched by the predetermined etchant is equal to or less than about 100 Å

/s (Angstroms per second).

10. The semiconductive device of claim 9, wherein

a difference between a respective content of tin (Sn) in the second composition and a respective content of tin (Sn) in the first composition is equal to or less than about 15 at. %.

11. The semiconductive device of claim 1, wherein

a respective thickness of each of the first and second semiconductive oxide layers is respectively in a range from about 5 Å

to about 600 Å

.

12. The semiconductive device of claim 1, wherein

a difference between a respective content of tin (Sn) in the second composition and a respective content of tin (Sn) in the first composition is equal to or less than about 15 at. %.

13. The semiconductive device of claim 1, wherein

the second semiconductive oxide further includes indium (In).

14. The semiconductive device of claim 1, wherein

each of the source electrode and the drain electrode includes a layer of copper, and

each of the source electrode and the drain electrode directly contacts the second semiconductive oxide layer.

15. A thin film transistor array panel comprising:

a substrate;

a gate electrode disposed on the substrate;

a gate insulating layer insulating the gate electrode;

a first semiconductive oxide layer and a second semiconductive oxide layer that both overlap the gate electrode and are insulated from the gate electrode by the gate insulating layer, the first and second semiconductive oxide layers being electrically connected to each other;

a source electrode connected to the second semiconductive oxide layer;

a drain electrode connected to the second semiconductive oxide layer and being spaced apart from the source electrode; and

a pixel electrode connected to the drain electrode,

wherein the second semiconductive oxide layer includes in operationally effective concentration at least one additional element not included in the first semiconductive oxide layer,

the at least one additional element is one of gallium (Ga), silicon (Si), niobium (Nb), hafnium (Hf), and germanium (Ge),

wherein the first semiconductive oxide layer is interposed between the gate insulating layer and the second semiconductive oxide layer, and

a content of the additional element is in a range from about 1 at. % to about 30 at. % relative to the 100 atomic percent composition of the second semiconductive oxide laver.

16. The thin film transistor array panel of claim 15, wherein

the first semiconductive oxide layer includes an indium (In)-zinc(Zn)-tin(Sn) oxide (IZTO), and

the second semiconductive oxide layer includes a zinc(Zn)-tin(Sn) oxide (ZTO).

17. The thin film transistor array panel of claim 16, wherein

the respective compositions of the first semiconductive oxide layer and of the second semiconductive oxide layer are simultaneously etchable by a same predetermined etchant, and

a difference between etch rates of the respective compositions of the first and second semiconductive oxide layers when being etched by the predetermined etchant is equal to or less than about 100 Å

/s (Angstroms per second).

18. The thin film transistor array panel of claim 17, wherein

a difference between a respective content of tin (Sn) of the second semiconductive oxide layer and a respective content of tin (Sn) of the first semiconductive oxide layer is equal to or less than about 15 at. %.

19. The thin film transistor array panel of claim 18, wherein

a respective thickness of each of the first semiconductive oxide layer and of the second semiconductive oxide layer is respectively in a range from about 5 Å

to about 600 Å

.

20. The thin film transistor array panel of claim 19, wherein

the second semiconductive oxide layer includes indium (In).

21. The thin film transistor array panel of claim 20, wherein

the source electrode and the drain electrode include a single layer of copper, and

the source electrode and the drain electrode directly contact the second semiconductive oxide layer.

22. The semiconductive device of claim 19, wherein

the first semiconductive oxide is an indium(In)-zinc(Zn)-tin(Sn) oxide (IZTO), and

the second semiconductive oxide is a zinc(Zn)-tin(Sn) oxide (ZTO).

23. The thin film transistor array panel of claim 15, wherein

the respective compositions of the first semiconductive oxide layer and of the second semiconductive oxide layer are simultaneously etchable by a same predetermined etchant, and

a difference between etch rates of the respective compositions of the first and second semiconductive oxide layers when being etched by the predetermined etchant is equal to or less than about 100 Å

/s (Angstroms per second).

24. The thin film transistor array panel of claim 23, wherein

a difference between a content of tin (Sn) of the second semiconductive oxide layer and a content of tin (Sn) of the first semiconductive oxide layer is equal to or less than about 15 at. %.

25. The thin film transistor array panel of claim 15, wherein

a respective thickness of each of the first semiconductive oxide layer and the second semiconductive oxide layer is respectively in a range from about 5 Å

to about 600 Å

.

26. The thin film transistor array panel of claim 15, wherein

a difference between a content of tin (Sn) of the second semiconductive oxide layer and a content of tin (Sn) of the first semiconductive oxide layer is equal to or less than about 15 at. %.

27. The thin film transistor array panel of claim 15, wherein

the second semiconductive oxide layer includes indium (In).

28. The thin film transistor array panel of claim 15, wherein

the source electrode and the drain electrode include a single layer of copper, and

the source electrode and the drain electrode directly contact the second semiconductive oxide layer.

29. A display device comprising:

a substrate;

a gate electrode positioned on the substrate;

a gate insulating layer positioned on or under the gate electrode;

a first semiconductive oxide and a second semiconductive oxide that both insulatively overlap with the gate electrode and contact each other;

a source electrode connected to the second semiconductive oxide;

a drain electrode connected to the second semiconductive oxide; and

a pixel electrode connected to the drain electrode,

wherein the second semiconductive oxide includes at least one additional element that is not included in the first semiconductive oxide,

the at least one additional element is one of gallium (Ga), silicon (Si), niobium (Nb), hafnium (Hf), and germanium (Ge),

wherein the first semiconductive oxide layer is interposed between the gate insulating layer and the second semiconductive oxide layer, and

a content of the at least one additional element is in a range from about 1 at. % to about 30 at. % of the content of the second semiconductive oxide.

30. The display device of claim 29, wherein

the first semiconductive oxide includes an indium(In)-zinc(Zn)-tin(Sn) oxide (IZTO), and

the second semiconductive oxide a zinc(Zn)-tin(Sn) oxide (ZTO).

31. The display device of claim 30, wherein

the first semiconductive oxide and the second semiconductive oxide are capable of being simultaneously etched by a predetermined etchant, and

a difference between respective etch rates of the first semiconductive oxide and the second semiconductive oxide when being etched by the predetermined etchant is equal to or less than about 100 Å

/s.

32. The display device of claim 31, wherein

a difference between a content of tin (Sn) of the second semiconductive oxide and a content of tin (Sn) of the first semiconductive oxide is equal to or less than about 15 at. %.

33. The display device of claim 32, wherein

the first and second semiconductive oxides are each in the form of a respective layer;

and

a respective thickness of the respective layer of each of the first semiconductive oxides is in a range from about 5 Å

to about 600 Å

.

34. The display device of claim 33, wherein

the second semiconductive oxide includes indium (In).

35. The display device of claim 34, wherein

the source electrode and the drain electrode include a single layer of copper, and

the source electrode and the drain electrode directly contact the second semiconductive oxide.

36. The display device of claim 29, wherein

the first semiconductive oxide includes an indium(In)-zinc(Zn)-tin(Sn) oxide (IZTO), and

the second semiconductive oxide includes a zinc(Zn)-tin(Sn) oxide (ZTO).

37. The display device of claim 29, wherein

the first and second semiconductive oxides are each capable of being etched by a same predetermined etchant, and

a difference between respective etch rates of the first second semiconductive oxides when being etched by the predetermined etchant is equal to or less than about 100 Å

/s.

38. The display device of claim 37, wherein

a difference between a content of tin (Sn) of the second semiconductive oxide and a content of tin (Sn) of the first semiconductive oxide is equal to or less than about 15 at. %.

39. The display device of claim 29, wherein

a thickness of each of the first semiconductive oxide and the second semiconductive oxide is in a range from about 5 Å

to about 600 Å

.

40. The display device of claim 29, wherein

a difference between a content of tin (Sn) of the second semiconductive oxide and a content of tin (Sn) of the first semiconductive oxide is equal to or less than about 15 at. %.

41. The display device of claim 29, wherein

the second semiconductive oxide includes indium (In).

42. The display device of claim 29, wherein

the source electrode and the drain electrode include a single layer of copper, and

the source electrode and the drain electrode directly contact the second semiconductive oxide layer.