Semiconductor device and structure

• US 8,686,428 B1
• Filed: 11/16/2012
• Issued: 04/01/2014
• Est. Priority Date: 11/16/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak, Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): CHIU, TSZ K
• Application Number:
  US13/678,588
• Time in Patent Office: 501 Days
• Field of Search: 257/347, 257/353, 257/67, 257/69, 257/E21.193, 257/99, 257/712, 257/88, 257/89, 257/98, 257/100, 257/173, 257/2, 257/355, 257/434, 257/619, 257/642, 257/686, 257/723, 257/777, 257/930
• US Class Current: 257/72
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device with an external surface, the device including: a substrate including first mono-crystal transistors; a second layer including second mono-crystal transistors, the second mono-crystal transistors overlaying the first mono-crystal transistors; and a plurality of thermal conduction paths from a plurality of the second layer locations to the external surface, wherein at least one of the thermal conduction paths includes an electrically nonconductive contact.

Claims

1. A device with an external surface, the device comprising:

a substrate comprising first mono-crystal transistors;

a second layer comprising second mono-crystal transistors, said second mono-crystal transistors overlaying said first mono-crystal transistors; and

a plurality of thermal conduction paths from a plurality of said second layer locations to said external surface,

wherein at least one of said thermal conduction paths comprises an electrically nonconductive contact, and

wherein a connection layer to said second mono-crystal transistors comprises said electrically non-conductive contact.

2. The device according to claim 1, wherein said second mono-crystal transistors are vertical transistors.

3. The device according to claim 1, further comprising:

a heat spreader layer between said first mono-crystal transistors and said second layer; and

a thermal conduction path between said heat spreader layer and said external surface.

4. The device according to claim 1, wherein said second mono-crystal transistors are JFET transistors.

5. The device according to claim 1, wherein a mobile system comprises the device.

6. The device according to claim 1, wherein said substrate comprises a first alignment mark and wherein said second mono-crystal transistors are aligned to said first alignment mark with less than 40 nm alignment error.

7. The device according to claim 1, comprising a connection through said second layer, wherein said second layer has a coefficient of thermal expansion, wherein said connection comprises material whose coefficient of thermal expansion is within 50% of the coefficient of thermal expansion of said second layer.

8. The device according to claim 1, comprising a plurality of connections that are interconnecting said second mono-crystal transistors, wherein a portion of said plurality of connections are in-between said first mono-crystal transistors and said second layer, and are aligned to said first mono-crystal transistors.

9. A device with an external surface, the device comprising:

a substrate comprising first mono-crystal transistors;

a second layer comprising second mono-crystal transistors, said second mono-crystal transistors overlaying said first mono-crystal transistors,

wherein said second layer thickness is less than 400 nm;

a heat spreader layer between said first mono-crystal transistors and said second layer; and

a thermal conduction path between said heat spreader and said external surface.

10. The device according to claim 9, wherein said second mono-crystal transistors are vertical transistors.

11. The device according to claim 9, comprising:

a plurality of thermal conduction paths from a plurality of said second layer locations to said external surface wherein at least one of said thermal conduction paths comprises an electrically nonconductive contact.

12. The device according to claim 9, wherein said second mono-crystal transistors are JFET transistors.

13. The device according to claim 9, wherein a mobile system comprises the device.

14. The device according to claim 9, wherein said substrate comprises a first alignment mark and wherein said second mono-crystal transistors are aligned to said first alignment mark with less than 40 nm alignment error.

15. The device according to claim 9, comprising a connection through said second layer, wherein said second layer has a coefficient of thermal expansion, wherein said connection comprises material whose coefficient of thermal expansion is within 50% of the coefficient of thermal expansion of said second layer.

16. The device according to claim 9, comprising a plurality of connections that are interconnecting said second mono-crystal transistors, wherein a portion of said plurality of connections are in-between said first mono-crystal transistors and said second layer, and are aligned to said first mono-crystal transistors.

17. A device with an external surface, the device comprising:

a substrate comprising first mono-crystal transistors;

a second layer comprising second mono-crystal transistors, said second layer overlaying said first mono-crystal transistors; and

a power grid to provide power to said second mono-crystal transistors,

wherein said power grid is designed to remove heat from said second layer,

wherein said power grid comprises a first power grid thermal conduction path to said external surface,

wherein said power grid comprises a plurality of second power grid thermal conduction paths to a plurality of said second mono-crystal transistors,

wherein at least one of said second power grid thermal conduction paths comprises an electrically nonconductive contact, and

wherein a connection layer to said second mono-crystal transistors comprises said electrically non-conductive contact.

18. The device according to claim 17, wherein said second mono-crystal transistors are vertical transistors.

19. The device according to claim 17, further comprising:

a heat spreader layer between said first mono-crystal transistors and said second layer; and

a third thermal conduction path between said heat spreader and said external surface.

20. The device according to claim 17, wherein said second mono-crystal transistors are JFET transistors.

21. The device according to claim 17, wherein a mobile system comprises the device.

22. The device according to claim 17, wherein said substrate comprises a first alignment mark and wherein said second mono-crystal transistors are aligned to said first alignment mark with less than 40 nm alignment error.

23. The device according to claim 17, comprising a connection through said second layer, wherein said second layer has a coefficient of thermal expansion, and wherein said connection comprises material whose coefficient of thermal expansion is within 50% of the coefficient of thermal expansion of said second layer.

24. The device according to claim 17, comprising a plurality of connections that are interconnecting said second mono-crystal transistors, wherein a portion of said plurality of connections are in-between said first mono-crystal transistors and said second layer, and are aligned to said first mono-crystal transistors.

25. A device with an external surface, the device comprising:

a substrate comprising first mono-crystal transistors,

wherein said first mono-crystal transistors are overlaid by at least one interconnection layer, said interconnection layer comprising aluminum or copper;

a second layer comprising second mono-crystal transistors, said second layer overlaying said first mono-crystal transistors,

wherein said second layer thickness is less than 400 nm, and

wherein said second layer has a coefficient of thermal expansion; and

a connection through said second layer,

wherein said connection comprises material whose coefficient of thermal expansion is within 50% of the coefficient of thermal expansion of said second layer.

26. The device according to claim 25, wherein said second mono-crystal transistors are vertical transistors.

27. The device according to claim 25, comprising:

a plurality of thermal conduction paths from a plurality of said second layer locations to said external surface, wherein at least one of said thermal conduction paths comprises an electrically nonconductive contact.

28. The device according to claim 25, further comprising:

a heat spreader layer between said first mono-crystal transistors and said second layer; and

a thermal conduction path between said heat spreader and said external surface.

29. The device according to claim 25, wherein said substrate comprises a first alignment mark and wherein said second mono-crystal transistors are aligned to said first alignment mark with less than 40 nm alignment error.

30. The device according to claim 25, comprising a plurality of connections that are interconnecting said second mono-crystal transistors, wherein a portion of said plurality of connections are in-between said first mono-crystal transistors and said second layer, and are aligned to said first mono-crystal transistors.