Memory device

• US 8,686,486 B2
• Filed: 03/21/2012
• Issued: 04/01/2014
• Est. Priority Date: 03/31/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Saito, Toshihiko
• Primary Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US13/425,674
• Publication Number:
  US 20120248434A1
• Time in Patent Office: 741 Days
• Field of Search: None
• US Class Current: 257/308
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line

Abstract

It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.

Claims

1. A memory device comprising:

a first wiring;

a first insulating layer over the first wiring, wherein the first insulating layer comprises a groove portion;

a semiconductor layer over the first insulating layer and in the groove portion, wherein the semiconductor layer is electrically connected to the first wiring;

a second insulating layer adjacent to the semiconductor layer in the groove;

a second wiring in the groove portion, wherein the second wiring is adjacent to the semiconductor layer with the second insulating layer interposed therebetween; and

a capacitor over the first insulating layer and the semiconductor layer, wherein the capacitor is electrically connected to the semiconductor layer,

wherein a top surface of the second wiring is positioned over a top surface of the first insulating layer.

2. The memory device according to claim 1, wherein the semiconductor layer comprises an oxide semiconductor.

3. The memory device according to claim 2, wherein the oxide semiconductor comprises indium, gallium, and zinc.

4. The memory device according to claim 1, wherein the semiconductor layer is provided on a side surface of the first insulating layer.

5. The memory device according to claim 1, further comprising a first conductive layer over the first insulating layer, wherein the semiconductor layer is provided over the first conductive layer.

6. The memory device according to claim 1, wherein the first wiring and the second wiring are orthogonal to each other.

7. The memory device according to claim 1,

wherein the first wiring is a bit line, and

wherein the second wiring is a word line.

8. The memory device according to claim 1, wherein a depth of the groove portion is 2 to 20 times as much as a width of the groove portion.

9. The memory device according to claim 1, further comprising a driver circuit below the first wiring.

10. A memory device comprising:

a first wiring;

a third insulating layer over the first wiring, wherein the third insulating layer comprises an opening;

a first conductive layer in the opening of the third insulating layer;

a first insulating layer over the third insulating layer, wherein the first insulating layer comprises a groove portion over the first conductive layer;

a semiconductor layer over the first insulating layer and the first conductive layer and in the groove portion, wherein the semiconductor layer is electrically connected to the first wiring through the first conductive layer;

a second insulating layer adjacent to the semiconductor layer;

a second wiring in the groove portion, wherein the second wiring is adjacent to the semiconductor layer with the second insulating layer interposed therebetween and provided over the first conductive layer with the semiconductor layer and the second insulating layer interposed therebetween;

a fourth insulating layer over the second wiring, wherein the fourth insulating layer comprises an opening over the first insulating layer;

a second conductive layer in the opening of the fourth insulating layer and over the semiconductor layer; and

a capacitor over the second conductive layer, wherein the capacitor is electrically connected to the semiconductor layer through the second conductive layer,

wherein a top surface of the second wiring is positioned over a top surface of the first insulating layer.

11. The memory device according to claim 10, wherein the semiconductor layer comprises an oxide semiconductor.

12. The memory device according to claim 11, wherein the oxide semiconductor comprises indium, gallium, and zinc.

13. The memory device according to claim 10, wherein the semiconductor layer is provided on a side surface of the first insulating layer.

14. The memory device according to claim 10, further comprising a third conductive layer over the first insulating layer, wherein the semiconductor layer is provided over the third conductive layer.

15. The memory device according to claim 10, wherein the first wiring and the second wiring are orthogonal to each other.

16. The memory device according to claim 10,

wherein the first wiring is a bit line, and

wherein the second wiring is a word line.

17. The memory device according to claim 10, wherein a depth of the groove portion is 2 to 20 times as much as a width of the groove portion.

18. The memory device according to claim 10, further comprising a driver circuit below the first wiring.

19. The memory device according to claim 10, wherein the first conductive layer and the second conductive layer are not overlapped with each other.

20. A memory device comprising:

a first wiring;

a third insulating layer over the first wiring, wherein the third insulating layer comprises an opening;

a first conductive layer in the opening of the third insulating layer;

a first insulating layer over the third insulating layer, wherein the first insulating layer comprises a groove portion over the first conductive layer;

a semiconductor layer over the first insulating layer and the first conductive layer and in the groove portion, wherein the semiconductor layer is electrically connected to the first wiring through the first conductive layer;

a second insulating layer adjacent to the semiconductor layer;

a second wiring in the groove portion, wherein the second wiring is adjacent to the semiconductor layer with the second insulating layer interposed therebetween and provided over the first conductive layer with the semiconductor layer and the second insulating layer interposed therebetween;

a fourth insulating layer over the second wiring, wherein the fourth insulating layer comprises an opening over the first insulating layer;

a second conductive layer in the opening of the fourth insulating layer and over the semiconductor layer;

a fifth insulating layer over the fourth insulating layer, wherein the fifth insulating layer comprises an opening over the second conductive layer; and

a capacitor in the opening of the fifth insulating layer, wherein the capacitor comprises;

a first electrode layer electrically connected to the semiconductor layer through the second conductive layer;

a dielectric layer; and

a second electrode layer surrounded by the first electrode layer with the dielectric layer interposed therebetween,

wherein a top surface of the second wiring is positioned over a top surface of the first insulating layer.

21. The memory device according to claim 20, wherein the semiconductor layer comprises an oxide semiconductor.

22. The memory device according to claim 21, wherein the oxide semiconductor comprises indium, gallium, and zinc.

23. The memory device according to claim 20, wherein the semiconductor layer is provided on a side surface of the first insulating layer.

24. The memory device according to claim 20, further comprising a third conductive layer over the first insulating layer, wherein the semiconductor layer is provided over the third conductive layer.

25. The memory device according to claim 20, wherein the first wiring and the second wiring are orthogonal to each other.

26. The memory device according to claim 20,

wherein the first wiring is a bit line, and

wherein the second wiring is a word line.

27. The memory device according to claim 20, wherein a depth of the groove portion is 2 to 20 times as much as a width of the groove portion.

28. The memory device according to claim 20, further comprising a driver circuit below the first wiring.

29. The memory device according to claim 20, wherein the first conductive layer and the second conductive layer are not overlapped with each other.