Semiconductor devices and electronic systems comprising floating gate transistors

• US 8,686,487 B2
• Filed: 06/14/2007
• Issued: 04/01/2014
• Est. Priority Date: 06/14/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej, Mouli, Chandra, Li, Di
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US11/763,335
• Publication Number:
  US 20080308858A1
• Time in Patent Office: 2,483 Days
• Field of Search: 257315-317, 257319-322, 257/324, 257/E21.209, 257/E29.29, 257/E29.3, 257/E29.129, 438/201, 438/211, 438/257, 438/260, 438/266
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10K 50/844 Encapsulations
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

Claims

1. A semiconductor device having at least one transistor comprising:

a source;

a drain;

a control gate; and

a floating gate comprising;

a first end portion proximate the source and the drain;

a second end portion proximate the control gate; and

an intermediate portion including a single nanowire extending between the first end portion and the second end portion, wherein the single nanowire has an average width less than about 50 nanometers, and wherein the intermediate portion has a smaller average cross-section than an average cross section of the first end portion.

2. The semiconductor device of claim 1, wherein the floating gate comprises a polysilicon material doped with a dopant.

3. The semiconductor device of claim 2, wherein the intermediate portion of the floating gate has an average concentration of the dopant differing from an average concentration of the dopant in the first end portion and an average concentration of the dopant in the second end portion.

4. The semiconductor device of claim 3, wherein a concentration of the dopant varies substantially continuously through the floating gate between the first end portion and the second end portion.

5. The semiconductor device of claim 1, wherein at least one surface of the control gate comprises a protrusion on the control gate, the protrusion at least partially disposed within a recess in a side of the floating gate.

6. The semiconductor device of claim 5, wherein the protrusion substantially fills the recess.

7. The semiconductor device of claim 1, wherein the single nanowire comprises a doped silicon material.

8. The semiconductor device of claim 1, wherein the single nanowire comprises a material selected from the group consisting of silicon, germanium, gallium, a III-V type semiconductor material, and a II-V type semiconductor material.

9. A semiconductor device having at least one transistor comprising:

a source;

a drain;

a control gate; and

a floating gate, comprising;

a first end portion proximate the source and the drain;

a second end portion proximate the control gate; and

an intermediate portion including a single nanowire extending between the first end portion and the second end portion, wherein the single nanowire has an average width less than about 50 nanometers;

wherein at least a portion of the control gate has a shape substantially complementary to a shape of at least a portion of the second end portion of the floating gate.

10. The semiconductor device of claim 9, wherein the control gate comprises at least one surface opposing an upper surface of the second end portion of the floating gate and at least one surface opposing a lateral side surface of the second end portion of the floating gate.

11. The semiconductor device of claim 10, wherein the control gate further comprises at least one surface opposing at least a portion of a lateral side surface of the intermediate portion of the floating gate.

12. The semiconductor device of claim 11, wherein the at least one surface of the control gate opposing the at least a portion of the lateral side surface of the intermediate portion of the floating gate is disposed on a protrusion of the control gate, the protrusion at least partially disposed in a recess of the floating gate at least partially defined by the at least a portion of the lateral side surface of the intermediate portion of the floating gate.

13. A semiconductor device having at least one transistor comprising:

a source;

a drain;

a control gate; and

a floating gate, comprising;

a first end portion proximate the source and the drain;

a second end portion proximate the control gate; and

an intermediate portion including a single nanowire extending between the first end portion and the second end portion, wherein the single nanowire has an average width less than about 50 nanometers, and wherein the floating gate has a dumbbell shape.

14. A semiconductor device having at least one transistor comprising an electrically isolated floating gate and a control gate capacitively coupled with the floating gate, the control gate having at least one surface opposing an upper surface of an end portion of the floating gate and at least one surface opposing a lateral side surface of a single nanowire of the floating gate, the lateral side surface of the single nanowire of the floating gate defining a recess in the floating gate wherein the single nanowire has an average width less than about 50 nanometers.

15. The semiconductor device of claim 14, wherein the at least one surface of the control gate opposing the lateral side surface of the floating gate at least partially comprises a protrusion of the control gate at least partially disposed within the recess of the floating gate.

16. The semiconductor device of claim 15, wherein the protrusion of the control gate substantially fills the recess of the floating gate.

17. The semiconductor device of claim 14, wherein the floating gate comprises a polysilicon material doped with a dopant.

18. The semiconductor device of claim 17, wherein an intermediate portion of the floating gate has an average concentration of the dopant differing from an average concentration of the dopant in a first end portion of the floating gate and an average concentration of the dopant in a second end portion of the floating gate.

19. The semiconductor device of claim 14, wherein the single nanowire comprises a single crystal.

20. The semiconductor device of claim 14, wherein the single nanowire comprises a metal selected from the group consisting of cobalt, copper, gold, nickel, platinum, and silver.

21. A semiconductor device having at least one transistor comprising an electrically isolated floating gate and a control gate capacitively coupled with the floating gate, the floating gate comprising a single nanowire extending between a first end portion of the floating gate and a second end portion of the floating gate, the control gate disposed at least partially over and around the second end portion of the floating gate and at least partially around a portion of the single nanowire, wherein the single nanowire has an average width less than about 50 nanometers.

22. The semiconductor device of claim 21, wherein at least a portion of the control gate has a shape substantially complementary to a shape of the second end portion of the floating gate.

23. The semiconductor device of claim 22, wherein the control gate comprises at least one surface opposing an upper surface of the second end portion of the floating gate and at least one surface opposing a lateral side surface of the second end portion of the floating gate.

24. The semiconductor device of claim 23, wherein the control gate further comprises at least one surface opposing at least a portion of a lateral side surface of the single nanowire.

25. The semiconductor device of claim 24, wherein the at least one surface of the control gate opposing the lateral side surface of the single nanowire is disposed on a protrusion of the control gate.

26. An electronic system comprising:

at least one electronic signal processor;

at least one semiconductor device configured to communicate electrically with the at least one electronic signal processor; and

at least one of an input device and an output device configured to communicate electrically with the at least one electronic signal processor, at least one of the at least one electronic signal processor and the at least one semiconductor device having at least one transistor comprising an electrically isolated floating gate and a control gate capacitively coupled with the floating gate, the control gate having at least one surface opposing an upper surface of an end portion of the floating gate and at least one surface opposing a lateral side surface of the floating gate, the lateral side surface of the floating gate defining a recess in the floating gate, wherein the floating gate of the at least one transistor further comprises;

an additional end portion proximate a source and a drain; and

an intermediate portion comprising a single nanowire disposed between the end portion and the additional end portion, wherein the single nanowire has an average width less than about 50 nanometers.

27. The electronic system of claim 26, wherein the electronic system comprises one of a computer, a computer hardware component, a server, a networking hardware component, a cellular telephone, a digital camera, a personal digital assistant, and a portable media player.

28. The electronic system of claim 27, wherein the input device comprises at least one of a pointing device, a keyboard, a touchpad, a touchscreen, and a button, and wherein the output device comprises at least one of a monitor, a display, a touchscreen, a printer, an audio output jack, and a speaker.

29. The electronic system of claim 26, wherein the at least one surface of the control gate opposing the lateral side surface of the floating gate at least partially comprises a protrusion of the control gate at least partially disposed within the recess of the floating gate.

30. The electronic system of claim 26, wherein the floating gate comprises a polysilicon material doped with a dopant.

31. The electronic system of claim 30, wherein an intermediate portion of the floating gate has an average concentration of the dopant differing from an average concentration of the dopant in a first end portion of the floating gate and an average concentration of the dopant in a second end portion of the floating gate.

32. The electronic system of claim 26, wherein the single nanowire comprises a nanotube.

33. The electronic system of claim 32, wherein the nanotube is selected from the group consisting of a single wall carbon nanotube and a multi-walled carbon nanotube.

34. An electronic system comprising:

at least one electronic signal processor;

at least one semiconductor device configured to communicate electrically with the at least one electronic signal processor; and

at least one of an input device and an output device configured to communicate electrically with the at least one electronic signal processor, at least one of the at least one electronic signal processor and the at least one semiconductor device having at least one transistor comprising an electrically isolated floating gate and a control gate capacitively coupled with the floating gate, the floating gate comprising a single nanowire having an average width less than about 50 nanometers extending between a first end portion of the floating gate and a second end portion of the floating gate, the control gate disposed at least partially over and around the second end portion of the floating gate and at least partially around a portion of the single nanowire.

35. The electronic system of claim 34, wherein the control gate comprises at least one surface opposing an upper surface of the second end portion of the floating gate and at least one surface opposing a lateral side surface of the second end portion of the floating gate.

36. The electronic system of claim 35, wherein the control gate further comprises at least one surface opposing at least a portion of a lateral side surface of the single nanowire.

37. The electronic system of claim 34, wherein the single nanowire is a substantially solid nanowire.

38. A method of forming a semiconductor device having at least one transistor, comprising:

forming a source and a drain;

forming a floating gate having a first end portion proximate to the source and the drain, a second end portion, and an intermediate portion including a single nanowire having an average width of less than about 50 nm extending between the first end portion and the second end portion, wherein the intermediate portion has an average cross-sectional area less than an average cross-sectional area of the first end portion; and

forming a control gate at least partially over and around at least the second end portion of the floating gate.

39. The method of claim 38, wherein forming a floating gate comprises:

forming the first end portion of the floating gate;

forming the second end portion of the floating gate over the first end portion of the floating gate;

forming an opening extending through the second end portion of the floating gate to the first end portion of the floating gate; and

filling the opening with a conductive material to form an intermediate portion of the floating gate extending between the first end portion and the second end portion.

40. The method of claim 39, further comprising:

forming a first portion of the control gate over the first end portion of the floating gate, wherein the second end portion of the floating gate is formed over the first portion of the control gate, and wherein forming the opening through the second end portion of the floating gate further comprises forming the opening through the first portion of the control gate; and

forming a second end portion of the control gate at least partially over and around at least the second end portion of the floating gate.

41. The method of claim 40, further comprising forming an inter-gate dielectric material on at least one surface of the first portion of the control gate within the opening prior to filling the opening with the conductive material.

42. The method of claim 38, wherein forming a floating gate comprises:

forming a conductive structure comprising polysilicon material doped with a dopant;

doping an intermediate portion of the conductive structure with an average concentration of the dopant differing from an average concentration of the dopant in a first end portion of the conductive structure and an average concentration of the dopant in a second end portion of the conductive structure; and

etching the conductive structure with an etchant at a rate at least partially dependent on the concentration of the dopant in the conductive structure.

43. The method of claim 38, further comprising forming the first end portion of the floating gate, and wherein forming the floating gate having an intermediate portion including the single nanowire comprises:

forming the single nanowire on a surface of the first end portion of the floating gate and establishing electrical contact between a first end of the single nanowire and the first end portion of the floating gate;

surrounding at least a portion of the single nanowire with a dielectric material; and

forming the second end portion of the floating gate over a second end of the single nanowire and establishing electrical contact between the second end of the single nanowire and the second end portion of the floating gate.

44. The method of claim 43, wherein forming the single nanowire on the surface of the first end portion of the floating gate includes growing the single nanowire using a catalytic structure.