High density FET with integrated Schottky

• US 8,686,493 B2
• Filed: 09/30/2008
• Issued: 04/01/2014
• Est. Priority Date: 10/04/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Thorup, Paul, Rexer, Christopher Lawrence
• Primary Examiner(s): ARORA, AJAY
• Application Number:
  US12/242,633
• Publication Number:
  US 20090090966A1
• Time in Patent Office: 2,009 Days
• Field of Search: 257328-330, 257/E27.081, 257/409
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode

Abstract

A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween.

Claims

1. A semiconductor structure including a monolithically integrated trench FET and Schottky diode, the semiconductor structure comprising:

a plurality of trenches extending into a semiconductor region of a first conductivity type;

a gate electrode in each trench;

first and second body regions of a second conductivity type over the semiconductor region between first and second pair of adjacent trenches, respectively;

a source region of the first conductivity type over the first body region;

a recess extending between each of the first and second adjacent trenches and terminating in the semiconductor region at a depth below the first and second body regions; and

an interconnect layer electrically contacting exposed surfaces of the source region and the first and second body regions in each recess, the interconnect layer further contacting the semiconductor region along a bottom of each recess to form a Schottky contact therebetween, the interconnect layer forming an anode terminal of the Schottky diode and a source electrode of the FET.

2. The semiconductor structure of claim 1 the first body region has an upper surface below an upper surface of the gate electrode, and the second body region vertically extends above the upper surface the gate electrode.

3. The semiconductor structure of claim 1 wherein each recess has tapered edges and is self aligned with the trenches.

4. The semiconductor structure of claim 1 further comprising:

a shield electrode in a lower portion of each trench below the gate electrode, the shield electrode being insulated from the semiconductor region by a shield dielectric;

an inter-electrode dielectric extending between the shield electrode and gate electrode in each trench; and

a gate dielectric lining upper trench sidewalls of each trench.

5. The semiconductor structure of claim 1 wherein the gate electrode is recessed in each trench and is capped with a dielectric material.

6. The semiconductor structure of claim 1 wherein the interconnect layer further comprises a barrier metal layer which forms a Schottky contact with the semiconductor region along a bottom of each recess.

7. The semiconductor structure of claim 1 further comprising a thick bottom dielectric below the gate electrode in each trench.

8. The semiconductor structure of claim 1 further comprising a plurality of heavy body regions of the second conductivity type over and in contact with the first body region.

9. The semiconductor structure of claim 1 wherein during operation, a conduction channel is formed in the first body region but not in the second body region.

10. The semiconductor structure of claim 1 wherein when the FET is turned on, a current flows through the first body region but not through the second body region.

11. The semiconductor structure of claim 1 further comprising a doped region in the semiconductor region along the bottom of each recess where the Schottky contact is formed.

12. A semiconductor structure comprising a monolithically integrated trench FET and Schottky diode, the semiconductor structure further comprising:

a plurality of trenches extending into a semiconductor region of a first conductivity type;

a gate electrode in each trench;

first and second body regions of a second conductivity type over the semiconductor region between a first and second pair of adjacent trenches, respectively;

source regions of the first conductivity type over the first body region;

a first recess extending between the first pair of trenches and terminating in the first body region at a depth below the source regions;

a second recess extending between the second pair of trenches and terminating in the semiconductor region at a depth below the second body regions; and

an interconnect layer electrically contacting exposed surfaces of the source regions and the first and second body regions in each of the first and second recesses, the interconnect layer further contacting the semiconductor region along a bottom of the second recess to form a Schottky contact therebetween, the interconnect layer forming an anode terminal of the Schottky diode and a source electrode of the FET.

13. The semiconductor structure of claim 12 further comprising:

a shield electrode in a lower portion of each trench below the gate electrode, the shield electrode being insulated from the semiconductor region by a shield dielectric;

an inter-electrode dielectric extending between the shield electrode and gate electrode in each trench; and

a gate dielectric lining upper trench sidewalls of each trench.

14. The semiconductor structure of claim 12 further comprising a thick bottom dielectric below the gate electrode in each trench.

15. A semiconductor structure, comprising:

a plurality of trenches extending into a semiconductor region of a first conductivity type;

a gate electrode in each trench;

one or more trench FET regions, each trench FET region including;

a first body region of a second conductivity type over the semiconductor region between a first pair of adjacent trenches;

a source region of the first conductivity type over the first body region; and

a first recess extending between the first pair of adjacent trenches and terminating in the first body region at a depth below the source region;

one or more Schottky regions, each Schottky region including;

a second body region of a second conductivity type over the semiconductor region between a second pair of adjacent trenches; and

a second recess extending between the second pair of adjacent trenches and terminating in the semiconductor region at a depth below the second body region, wherein the second body region extends to a top region of the second recess; and

an interconnect layer extending into the first recess and the second recess, wherein the interconnect layer contacts a bottom of the second recess in the Schottky region to form a Schottky diode, and the interconnect layer contacts surfaces of the source region and the first body region in the trench FET region, the interconnect layer forming a terminal of the Schottky diode and an electrode of the FET.

16. The semiconductor structure of claim 15, wherein the number of the trench FET regions is greater or less than the number of the Schottky regions.

17. A semiconductor structure, comprising:

a plurality of trenches extending into a semiconductor region of a first conductivity type;

a gate electrode in each trench;

one or more trench FET regions, each trench FET region including;

a first body region of a second conductivity type over the semiconductor region between a first pair of adjacent trenches;

a source region of the first conductivity type over the first body region; and

a first recess extending between the first pair of adjacent trenches and terminating in the semiconductor region at a depth below the first body region;

one or more integrated device regions, each integrated device region including;

a second body region of a second conductivity type over the semiconductor region between a second pair of adjacent trenches; and

a second recess extending between the second pair of adjacent trenches and terminating in the semiconductor region at a depth below the second body region, wherein the second body region extends to a top region of the second recess; and

an interconnect layer extending into the first recess and the second recess and contacting the semiconductor region at bottoms of the first recess and the second recess to form Schottky contacts, wherein the interconnect layer contacts surfaces of the source region and the first body region in the trench FET region and contacts a surface of the second body region in the integrated device region.

18. The semiconductor structure of claim 17, wherein the number of the trench FET regions is greater or less than the number of the integrated device regions.