Power semiconductor device

• US 8,686,495 B1
• Filed: 03/06/2013
• Issued: 04/01/2014
• Est. Priority Date: 09/12/2012
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Saito, Wataru
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US13/787,726
• Publication Number:
  US 20140070852A1
• Time in Patent Office: 391 Days
• Field of Search: 257329-332, 257/500, 257/502, 438/259
• US Class Current: 257/330
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference

Abstract

According to one or more embodiments of the present invention, a power semiconductor device comprise a plurality of gate electrodes, first to third electrodes, and first to fifth semiconductor layers The second semiconductor layer is formed on the first semiconductor layer. A plurality of the third semiconductor layers are formed in the second semiconductor layer and arranged in a direction perpendicular to the stacking direction. The fourth semiconductor layer is formed on the second semiconductor layer. The fifth semiconductor layer is formed on the fourth semiconductor layer. The gate electrodes are formed above the second semiconductor layer and each gate electrode is arranged between the adjacent third semiconductor layers. The first electrodes are formed below the gate electrodes. One of the first electrodes is connected to the gate electrode. One of the first electrodes is connected to the third electrode.

Claims

1. A power semiconductor device, comprising:

a first semiconductor layer;

a second semiconductor layer of a first conductivity type formed on the first semiconductor layer;

a plurality of third semiconductor layers of a second conductivity type formed in the second semiconductor layer and arranged at a predetermined interval along a direction perpendicular to the stacking direction of the first and the second semiconductor layers;

a fourth semiconductor layer of the second conductivity type formed on the second semiconductor layer;

fifth semiconductor layers of the first conductivity type formed on the fourth semiconductor layer;

a plurality of gate electrodes, at least a part of which are formed above the second semiconductor layer and a part of each gate electrode is arranged between the two of the third semiconductor layers adjacent to each other;

a plurality of first electrodes, each of which is formed below one of the gate electrodes;

a second electrode electrically connected to the first semiconductor layer; and

a third electrode electrically connected to the fifth semiconductor layer;

wherein at least one of the first electrodes is electrically connected to one of the gate electrodes, and at least another one of the first electrodes is electrically connected to the third electrode.

2. The power semiconductor device according to claim 1, wherein

a plurality of the first electrodes are electrically connected to the gate electrodes, and

a plurality of the first electrodes are electrically connected to the third electrodes, and

the first electrodes electrically connected to the gate electrode and the first electrodes electrically connected to the third electrodes are arranged alternately.

3. The power semiconductor device according to claim 1, wherein

at least one of the first electrodes electrically connected to the gate electrode adjoins to the first electrode electrically connected to the third electrode.

4. The power semiconductor device according to claim 1, wherein

at least one of the first electrodes electrically connected to the gate electrode is arranged between the first electrodes electrically connected to the third electrode.

5. The power semiconductor device according to claim 1, wherein

at least one of the first electrodes electrically connected to the third electrode is arranged between the first electrodes electrically connected to the gate electrodes.

6. The power semiconductor device according to claim 1, wherein

the plurality of the gate electrodes are arranged along the direction to which the third semiconductor layers are arranged.

7. The power semiconductor device according to claim 1, wherein

the plurality of the gate electrodes are arranged along a direction that is perpendicular to the stacking direction and perpendicular to the direction to which the third semiconductor layers are arranged.

8. The power semiconductor device according to claim 7, wherein

the pitch by which the third semiconductor layers are arranged is larger than the pitch by which the first electrodes are arranged.

9. The power semiconductor device according to claim 1, wherein

the plurality of the third semiconductor layers intersect with each other and constitute a mesh form.

10. The power semiconductor device according to claim 1, wherein

the concentration of the dopants in the portion above the lower end of the first electrode in the second semiconductor layer is higher than the concentration of the dopants in the portion below the lower end of the first electrode in the second semiconductor layer.

11. A power semiconductor device, comprising:

a first semiconductor layer;

a second semiconductor layer of a first conductivity type formed on the first semiconductor layer;

a plurality of third semiconductor layers of a second conductivity type formed in the second semiconductor layer and arranged at a predetermined interval along a direction perpendicular to the stacking direction of the first and the second semiconductor layers;

a fourth semiconductor layer of the second conductivity type formed on the second semiconductor layer;

fifth semiconductor layers of the first conductivity type formed on the fourth semiconductor layer;

a plurality of gate electrodes, at least a part of which are formed above the second semiconductor layer and a part of each gate electrode is arranged between the two of the third semiconductor layers adjacent to each other;

a plurality of first electrodes, each of which is formed below one of the gate electrodes;

a second electrode electrically connected to the first semiconductor layer; and

a third electrode electrically connected to the fifth semiconductor layer;

wherein at least one of the first electrodes has a same electric potential as one of the gate electrodes, and at least another one of the first electrodes has a same electric potential as the third electrode.

12. The power semiconductor device according to claim 11, wherein

a plurality of the first electrodes are electrically connected to the gate electrodes, and

a plurality of the first electrodes are electrically connected to the third electrodes, and

wherein

the first electrodes electrically connected to the gate electrode and the first electrodes electrically connected to the third electrodes are arranged alternately.

13. The power semiconductor device according to claim 11, wherein

at least one of the first electrodes electrically connected to the gate electrode adjoins to the first electrode electrically connected to the third electrode.

14. The power semiconductor device according to claim 11, wherein

the plurality of the gate electrodes are arranged along the direction to which the third semiconductor layers are arranged.

15. The power semiconductor device according to claim 11, wherein

the plurality of the gate electrodes are arranged along a direction that is perpendicular to the stacking direction and perpendicular to the direction to which the third semiconductor layers are arranged.