Silicide formation and associated devices

• US 8,686,516 B2
• Filed: 06/17/2013
• Issued: 04/01/2014
• Est. Priority Date: 09/08/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hung-Ming, Chang, Chih-Hao, Yu, Chih-Hao
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US13/919,459
• Publication Number:
  US 20140001574A1
• Time in Patent Office: 288 Days
• Field of Search: 257/349
• US Class Current: 257/410
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Improved silicide formation and associated devices are disclosed. An exemplary semiconductor device includes a semiconductor substrate, a fin structure disposed over the semiconductor substrate and having spaced source and drain regions extending outwardly from a channel region, and a gate structure disposed on a portion of the fin structure, the gate structure engaging the fin structure adjacent to the channel region. The device also includes a first silicide layer disposed on the fin structure, the first silicide layer extending outwardly from the gate structure along a top portion of the source region and a second silicide layer disposed on the fin structure, the second silicide layer extending outwardly from the gate structure along a top portion of the drain region. Further, the device includes a source contact conductively coupled to the first silicide layer and a drain contact conductively coupled to the second silicide layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a fin structure disposed over the semiconductor substrate and having spaced source and drain regions extending outwardly from a channel region defined between the source and drain regions;

a gate structure disposed on a portion of the fin structure, the gate structure engaging the fin structure adjacent to the channel region and between the source region and the drain region;

a first silicide layer disposed on the fin structure, the first silicide layer extending outwardly from the gate structure along a top portion of the source region;

a second silicide layer disposed on the fin structure, the second silicide layer extending outwardly from the gate structure along a top portion of the drain region;

a source contact conductively coupled to the first silicide layer and configured to transfer current to the source region; and

a drain contact conductively coupled to the second silicide layer and configured to transfer current away from the drain region.

2. The semiconductor device of claim 1, further including epitaxial growths in the source and drain regions of the fin structure on each side of the gate structure, the epitaxial growths imparting tensile strain to the channel region.

3. The semiconductor device of claim 1, further including spacers disposed on sidewalls of the gate structure and traversing the fin structure, the spacers being interposed between the sidewalls and the first and second silicide layers.

4. The semiconductor device of claim 1, further including an ILD layer disposed over the fin and gate structures, the source and drain contacts extending through respective contact holes in the ILD layer, and the contact holes having high aspect ratios.

5. The semiconductor device of claim 1, wherein the gate structure includes a high-k dielectric layer.

6. The semiconductor device of claim 1, wherein the gate structure includes a metal gate electrode.

7. The semiconductor device of claim 6, wherein the metal gate electrode is one of aluminum, copper, tungsten, and titanium.

8. A semiconductor device, comprising:

a semiconductor substrate;

a fin-like field effect transistor (FinFET) that includes a fin structure and a gate structure, the fin structure extending upwardly from the semiconductor substrate and including a channel region interposed between spaced source and drain regions, and the gate structure engaging the fin structure adjacent the channel region, the gate structure including;

a high-k dielectric material disposed over the channel region;

an opening over the high-k dielectric material and the first channel region; and

a metal gate electrode disposed in the opening;

a first silicide layer disposed on the fin structure, the first silicide layer extending outwardly from the gate structure along a top portion of the source region;

a second silicide layer disposed on the fin structure, the second silicide layer extending outwardly from the gate structure along a top portion of the drain region;

a source contact conductively coupled to the first silicide layer and configured to transfer current to the source region; and

a drain contact conductively coupled to the second silicide layer and configured to transfer current away from the drain region.

9. The semiconductor device of claim 8, wherein the gate structure engages the fin structure on three different surfaces of the fin structure.

10. The semiconductor device of claim 8, further including epitaxial growths in the source and drain regions of the fin structure on each side of the gate structure, the epitaxial growths imparting tensile strain to the channel region.

11. The semiconductor device of claim 8, further including spacers disposed on sidewalls of the gate structure and traversing the fin structure, the spacers being interposed between the sidewalls and the first and second silicide layers.

12. The semiconductor device of claim 8, further including an ILD layer disposed over the fin and gate structures, the source and drain contacts extending through respective contact holes in the ILD layer, and the contact holes having high aspect ratios.

13. A semiconductor device, comprising:

a semiconductor substrate having first and second trenches formed therein, the first and second trenches being spaced apart so as to form a fin structure extending upwardly from the substrate, the fin structure having spaced spaced source and drain regions and a channel region defined therebetween;

respective first and second isolation features partially filling the first and second trenches and surrounding a bottom portion of the fin structure;

a gate structure engaging three surfaces of the fin structure adjacent to the channel region;

a first silicide layer disposed on the fin structure, the first silicide layer extending outwardly from the gate structure along a top portion of the source region;

a second silicide layer disposed on the fin structure, the second silicide layer extending outwardly from the gate structure along a top portion of the drain region;

a source contact conductively coupled to the first silicide layer and configured to transfer current to the source region; and

a drain contact conductively coupled to the second silicide layer and configured to transfer current away from the drain region.

14. The semiconductor device of claim 13, wherein the first and second isolation features are multi-layer structures each having a liner layer and a filling layer.

15. The semiconductor device of claim 13, further including epitaxial growths in the source and drain regions of the fin structure on each side of the gate structure, the epitaxial growths imparting tensile strain to the channel region.

16. The semiconductor device of claim 13, further including spacers disposed on sidewalls of the gate structure and traversing the fin structure, the spacers being interposed between the sidewalls and the first and second silicide layers.

17. The semiconductor device of claim 13, wherein the gate structure includes a high-k dielectric layer.

18. The semiconductor device of claim 13, wherein the gate structure includes a metal gate electrode.

19. The semiconductor device of claim 18, wherein the metal gate electrode is one of aluminum, copper, tungsten, and titanium.

20. The semiconductor device of claim 13, further including an ILD layer disposed over the fin and gate structures, the source and drain contacts extending through respective contact holes in the ILD layer, and the contact holes having high aspect ratios.