Semiconductor trench inductors and transformers

• US 8,686,522 B2
• Filed: 10/13/2011
• Issued: 04/01/2014
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Webb, Bucknell C.
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): KLEIN, JORDAN M
• Application Number:
  US13/272,485
• Publication Number:
  US 20130093032A1
• Time in Patent Office: 901 Days
• Field of Search: 257/E29.323, 257/E21.022, 257421-427, 257/659, 438/3, 438/48
• US Class Current: 257/421
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Semiconductor trench inductor and transformer structures are provided, which include thin film conductive layers and magnetic layers formed within trenches etched in semiconductor substrates. Semiconductor trench devices effectively provide vertical oriented inductor and transformer structures whereby conductive coils and magnetic layers are vertically oriented on edge within trenches, thereby providing a space-saving compact design, and which allows the conductive layers within the trench to be enclosed by magnetic material, thereby providing a density of magnetic material that increases the storable energy density.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a trench formed in the semiconductor substrate, the trench defined by sidewalls and a bottom surface;

a magnetic layer formed in the trench, the magnetic layer conformally lining the sidewalls and bottom surface of the trench;

an insulating layer conformally lining the magnetic layer in the trench;

a first conductor layer formed in the trench, wherein the insulating layer electrically insulates the first conductor layer from the magnetic layer in the trench; and

an upper magnetic layer formed on the substrate and covering the trench, wherein the upper magnetic layer and the magnetic layer in the trench form a closed loop of magnetic material that encircles as least a portion of the first conductor layer formed in the trench, wherein the upper magnetic layer is electrically insulated from all conductor material in the trench.

2. The semiconductor device of claim 1, wherein the first conductor layer is a conformal layer that conformally lines the insulating layer in the trench.

3. The semiconductor device of claim 1, wherein the magnetic layer in the trench and the upper magnetic layer each comprises a multilayer structure comprising a plurality of sequentially formed magnetic and insulating material layers.

4. The semiconductor device of claim 1, wherein the trench comprises at least one bent portion.

5. The semiconductor device of claim 4, wherein the trench comprise a least one bent portion wherein at least a portion of the trench is U-shaped.

6. The semiconductor device of claim 1, further comprising:

a second insulating layer and a second conductor layer formed in the trench, wherein the second conductor layer is electrically isolated from first conductor layer by the second insulating layer, and

wherein the upper magnetic layer and the magnetic layer in the trench form a closed loop of magnetic material that encircles as least a portion of the first and second conductor layers formed in the trench, wherein the upper magnetic layer is electrically insulated from the first and second conductor layers in the trench.

7. The semiconductor device of claim 6, further comprising a first input pad, a second input pad, a first output pad and a second output pad, formed on the substrate surface, wherein the first input and output pads are connected to opposing end regions of the first conductor layer in the trench, and wherein the second input and output pads are connected to opposing end regions of the second conductor layer.

8. The semiconductor device of claim 7, further comprising an electrical connection that electrically connects the first output pad of the first conductor layer to the second input pad of the second conductor layer.

9. The semiconductor device of claim 1, wherein the trench is formed on back non-active side of the semiconductor substrate.

10. An integrated circuit chip, comprising an integrated circuit having one or more of the semiconductor device as recited in claim 1.

11. A semiconductor device, comprising:

a semiconductor substrate;

a first trench and second trench formed in the semiconductor substrate, the first and second trenches defined by sidewalls and a bottom surface;

a magnetic layer formed over the semiconductor substrate, the magnetic layer conformally lining the sidewalls and bottom surfaces of the first and second trenches, wherein the magnetic layer is continuous between the first trench and the second trench;

an insulating layer conformally lining the magnetic layer in the first and second trenches;

a first conductor formed in each of the first and second trenches, wherein the first conductor in each of the first and second trenches is electrically insulated from the magnetic layer by the insulating layer, and

an upper magnetic layer formed on the substrate and covering the first trench and the second trench, wherein the upper magnetic layer and the magnetic layer within the first and second trenches form a closed loop of magnetic material that encircles as least a portion of the first conductors formed in each of the first and second trenches, wherein the upper magnetic layer is electrically insulated from all conductor material in the first and second trenches.

12. The semiconductor device of claim 11, wherein the first conductor in each of the first and second trenches is a conformal conductive layer that conformally lines the insulating layer in the trenches.

13. The semiconductor device of claim 11, wherein the magnetic layer in the trenches and the upper magnetic layer each comprises a multilayer structure comprising a plurality of sequentially formed magnetic and insulating material layers.

14. The semiconductor device of claim 11, wherein the first and second trenches are disposed adjacent to each other and comprises at least one bent portion.

15. The semiconductor device of claim 14, wherein the first and second trenches comprise the least one bent portion forming a U-shaped trench structure.

16. The semiconductor device of claim 11, further comprising:

a second insulating layer and a second conductor formed in each of the first and second trenches, wherein the second conductor is electrically isolated from first conductor by the second insulating layer, and

wherein the upper magnetic layer and the magnetic layer in the trenches form a closed loop of magnetic material that encircles as least a portion of the first and second conductors formed in the trench, wherein the upper magnetic layer is electrically insulated from the first and second conductors in each of the first and second trenches.

17. The semiconductor device of claim 16, further comprising a first input pad, a second input pad, a third input pad, fourth input pad, a first output pad, a second output pad, a third output pad, and a fourth output pad formed on the semiconductor substrate surface, wherein the first input and output pads are connected to opposing end regions of the first conductor in the first trench, wherein the second input and output pads are connected to opposing end regions of the second conductor in the first trench wherein the third input and output pads are connected to opposing end regions of the first conductor in the second trench, and wherein the fourth input and output pads are connected to opposing end regions of the second conductor in the second trench.

18. The semiconductor device of claim 11, wherein the first and second trenches are formed on back non-active side of the semiconductor substrate.

19. An integrated circuit chip, comprising an integrated circuit having one or more of the semiconductor device as recited in claim 11.

20. The semiconductor device of claim 11, wherein the upper magnetic layer is dome-shaped.