Compliant monopolar micro device transfer head with silicon electrode

• US 8,686,542 B2
• Filed: 03/14/2013
• Issued: 04/01/2014
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Golda, Dariusz, Bibl, Andreas
• Primary Examiner(s): Coleman, William D
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US13/828,117
• Publication Number:
  US 20140008813A1
• Time in Patent Office: 383 Days
• Field of Search: 257/619, 257/623, 257/739, 257/774, 438/703, 438/739
• US Class Current: 257/619
• CPC Class Codes: B32B 38/18 Handling of layers or the laminate
• CPC Class Codes: B81C 99/002 Apparatus for assembling MEMS, e.g. micromanipulators micromanipulators per se B25J7/00
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 156/17 Surface bonding means and/or assemblymeans with work feeding or handling means

Abstract

A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.

Claims

1. A micro device transfer head array comprising:

a base substrate;

an array of electrostatic transfer heads, each electrostatic transfer head including a silicon electrode that is deflectable into a space between the base substrate and the silicon electrode, and a dielectric material covering a top surface of the silicon electrode.

2. The micro device transfer head array of claim 1, wherein each silicon electrode is deflectable into the same space.

3. The micro device transfer head array of claim 2, wherein the same space is a cavity in the base substrate.

4. The micro device transfer head array of claim 1, wherein each silicon electrode is deflectable into a separate space.

5. The micro device transfer head array of claim 4, wherein each separate space is a separate cavity in the base substrate.

6. The micro device transfer head array of claim 1, wherein the array of electrostatic transfer heads comprises:

a first array of electrostatic transfer heads in electrical connection with a first bus interconnect; and

a second array of electrostatic transfer heads in electrical connection with a second bus interconnect.

7. The micro device transfer head array of claim 6, wherein the array of electrostatic transfer heads comprises:

a first plurality of trace interconnects electrically connecting the first array of electrostatic transfer heads with the first bus interconnect; and

a second plurality of trace interconnects electrically connecting the second array of electrostatic transfer heads with the second bus interconnect.

8. The micro device transfer head array of claim 7, wherein the first and second plurality of trace interconnects are silicon trace interconnects, and the first and second bus interconnects are silicon bus interconnects.

9. The micro device transfer head array of claim 6, further comprising a first voltage source connection in electrical connection with the first bus interconnect, and a second voltage source connection in electrical connection with the second bus interconnect.

10. The micro device transfer head array of claim 9, wherein the first voltage source connection comprises a via extending through the first bus interconnect and the base substrate, and the second voltage source connection comprises a via extending through the second bus interconnect and the base substrate.

11. The micro device transfer head array of claim 1, wherein each electrostatic transfer head is configured to pick up an individual micro device of 1 to 100 μ

m scale.

12. The micro device transfer head of claim 1, wherein the dielectric material covering the top surface of the silicon electrode has a thickness between 0.5-10 μ

m.

13. The micro device transfer head of claim 1, wherein the silicon electrode include a silicon electrode lead and a silicon mesa structure.

14. The micro device transfer head of claim 13, wherein the mesa structure is less than 20 μ

m thick.

15. The micro device transfer head of claim 13, wherein the mesa structure is less than 10 μ

m thick.

16. The micro device transfer head of claim 1, wherein the silicon electrode is doped.

17. The micro device transfer head of claim 1, further comprising an oxide layer on a bottom surface of the silicon electrode.

18. The micro device transfer head of claim 1, wherein the dielectric material comprises an oxide selected from the group consisting of SiO₂, Al₂O₃, Ta₂O₅, HfO₂, and RuO₂.

19. The micro device transfer head of claim 1, further comprising a trace interconnect electrically connecting the array of electrostatic transfer heads with a bus interconnect, and a voltage source connection in electrical connection with the bus interconnect.

20. The micro device transfer head array of claim 19, wherein the voltage source connection comprises a via extending through the bus interconnect and the base substrate.