Semiconductor package substrates having layered circuit segments, and related methods

• US 8,686,568 B2
• Filed: 09/27/2012
• Issued: 04/01/2014
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Wang, Sheng-Ming, Kuo, Yen-Hua, Feng, Hsiang-Ming
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): NGUYEN, DILINH P
• Application Number:
  US13/629,397
• Publication Number:
  US 20140084480A1
• Time in Patent Office: 551 Days
• Field of Search: 257/621, 257/774, 257/730, 257/731, 257/782, 257/786, 257/737, 257/738, 257/784, 257/E21.597, 438/629, 438/637, 438/639, 438/640, 438/667, 438/668, 438/672, 438/675, 438/700, 438/701, 438/713, 438/978, 438/118, 438/617, 438/612, 438/666, 438/613
• US Class Current: 257/774
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.

Claims

1. A semiconductor package, comprising:

a substrate, the substrate comprising

a core having a plurality of through holes and defining a first surface;

a plurality of circuit segments disposed on the core, each of the circuit segments including a first patterned metal layer on the first surface, an intermediate metal layer on the first patterned metal layer, a barrier layer on the intermediate metal layer, and an upper metal pattern on the barrier layer; and

a plurality of conductive pillars disposed in the through holes of the core and connected to the circuit segments, wherein an end of each conductive pillar protrudes from the first surface of the core such that an end surface of each conductive pillar is coplanar with a surface of a corresponding portion of the barrier layer, and wherein the upper metal pattern covers the end surfaces of the conductive pillars and the coplanar surface of the barrier layer.

2. The semiconductor package of claim 1, wherein lateral surfaces of the first patterned metal layer, the intermediate metal layer, the barrier layer, and the upper metal pattern are coplanar.

3. The semiconductor package of claim 1, wherein the conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.

4. The semiconductor package of claim 1, wherein the first patterned metal layer, the intermediate metal layer, and the barrier layer of each circuit segment each include a portion that is annular and that circumscribes one of the conductive pillars.

5. The semiconductor package of claim 1, further comprising a protection layer disposed on the circuit segments, wherein the protection layer has a plurality of openings to expose portions of the circuit segments.

6. The semiconductor package of claim 5, further comprising a surface finish layer disposed on the exposed portions of the circuit segments.

7. The semiconductor package of claim 1, wherein an opposite end of each conductive pillar protrudes from a second surface of the core such that an opposite end surface of each conductive pillar is coplanar with a surface of a corresponding portion of the barrier layer.

8. The semiconductor package of claim 7, wherein a lower metal pattern covers the opposite end surfaces of the conductive pillars and the coplanar surface of the barrier layer.

9. A semiconductor package, comprising:

a substrate, the substrate comprising

a core having a plurality of through holes and defining a first surface;

a plurality of circuit segments disposed on the core, each of the circuit segments including a first patterned metal layer on the first surface, an intermediate metal layer on the first patterned metal layer, a barrier layer on the intermediate metal layer, and an upper metal pattern on the barrier layer, wherein lateral surfaces of the first patterned metal layer, the intermediate metal layer, the barrier layer, and the upper metal pattern are coplanar; and

a plurality of conductive vias disposed in the through holes of the core and connected to the circuit segments;

wherein an end of each conductive via protrudes from the first surface of the core such that an end surface of each conductive via is coplanar with a surface of a corresponding portion of the barrier layer, and wherein the upper metal pattern covers the end surfaces of the conductive vias and the coplanar surface of the barrier layer.

10. The semiconductor package of claim 9, further comprising a protection layer disposed on the circuit segments, wherein the protection layer has a plurality of openings to expose portions of the circuit segments.

11. The semiconductor package of claim 10, further comprising a surface finish layer disposed on the exposed portions of the circuit segments.

12. The semiconductor package of claim 9, wherein an opposite end of each conductive pillar protrudes from a second surface of the core such that an opposite end surface of each conductive pillar is coplanar with a surface of a corresponding portion of the barrier layer.

13. The semiconductor package of claim 12, wherein a lower metal pattern covers the opposite end surfaces of the conductive pillars and the coplanar surface of the barrier layer.

14. A method for making a semiconductor package substrate, the method comprising:

disposing a first metal layer on a core;

forming a plurality of through holes penetrating the core and the first metal layer;

forming an intermediate metal layer in the through holes and on the first metal layer;

forming a barrier layer on the intermediate metal layer;

applying a conductive material on the barrier layer to form a surface plating portion and in the through holes to form a plurality of conductive pillars;

removing the surface plating portion until the barrier layer is exposed;

forming an upper metal pattern on the exposed barrier layer and the conductive pillars; and

removing portions of the barrier layer, the intermediate metal layer and the first metal layer that are not covered by the upper metal pattern so as to form a plurality of circuit segments;

wherein an end of each conductive pillar protrudes from a first surface of the core such that an end surface of each conductive pillar is coplanar with a surface of a corresponding portion of the barrier layer, and wherein the upper metal pattern covers the end surfaces of the conductive pillars and the coplanar surface of the barrier layer.

15. The method of claim 14, wherein the upper metal pattern is formed by:

forming a photoresist pattern on the barrier layer, wherein the photoresist pattern has a plurality of openings;

applying a conductive material in the openings of the photoresist pattern to form the upper metal pattern; and

stripping the photoresist pattern.

16. The method of claim 14, further comprising forming a protection layer on the circuit segments, wherein the protection layer has a plurality of openings to expose portions of the circuit segments.

17. The method of claim 16, further comprising forming a surface finish layer on the exposed portions of the circuit segments.

18. The method of claim 14, wherein the conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.

19. The method of claim 14, wherein the barrier layer is nickel.