Input device receiver path and transmitter path error diagnosis

• US 8,686,735 B2
• Filed: 02/16/2011
• Issued: 04/01/2014
• Est. Priority Date: 02/16/2011
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Weinerth, John, Shahparnia, Shahrooz, Pant, Vivek, Reynolds, Joseph Kurth
• Primary Examiner(s): Phan, Huy Q
• Assistant Examiner(s): DICKINSON, DUSTIN R
• Application Number:
  US13/028,876
• Publication Number:
  US 20120207244A1
• Time in Patent Office: 1,140 Days
• Field of Search: 324/522, 324/523, 324/527, 324/649, 324/658, 324/659, 324/665, 324/679, 324/686
• US Class Current: 324/519
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: H03K 17/002 Switching arrangements with several input- or output terminals code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 17/9622 using a plurality of detectors, e.g. keyboard
• CPC Class Codes: H03K 2217/960775 Emitter-receiver or "fringe" type detection, i.e. one or more field emitting electrodes and corresponding one or more receiving electrodes

Abstract

An input device comprises a processing system coupled with a plurality of receiver paths. The processing system comprises a first capacitor and a bypass switch. The first capacitor is configured to be selectively coupled with the plurality of receiver paths. The bypass switch is configured for bypassing the first capacitor. The processing system is configured to selectively couple a first receiver path of the plurality of receiver paths with the first capacitor; acquire a measurement of a first resulting signal from at least one of the first receiver path or a second receiver path of the plurality of receiver paths while the first receiver path is coupled with the first capacitor and while the bypass switch is not bypassing the first capacitor; and determine whether the first receiver path is ohmically coupled with the second receiver path based on the measurement of the first resulting signal.

Claims

1. An input device comprising:

a plurality of receiver paths; and

a processing system coupled with said plurality of receiver paths, said processing system comprising;

a first capacitor configured to be selectively coupled with said plurality of receiver paths; and

a bypass switch configured for bypassing said first capacitor,

wherein said processing system is configured to;

selectively couple a first receiver path of said plurality of receiver paths with said first capacitor;

acquire a measurement of a first resulting signal from at least one of said first receiver path or a second receiver path of said plurality of receiver paths while said first receiver path is coupled with said first capacitor and while said bypass switch is not bypassing said first capacitor; and

determine whether said first receiver path is ohmically coupled with said second receiver path based on said measurement of said first resulting signal.

2. The input device of claim 1, wherein said processing system further comprises a second capacitor and a third capacitor configured to be selectively coupled with said plurality of receiver paths, and wherein said bypass switch is further configured to bypass said second and third capacitors.

3. The input device of claim 1, wherein said processing system further comprises:

a second capacitor and a third capacitor configured to be selectively coupled with said plurality of receiver paths;

wherein said processing system is further configured to;

couple said first receiver path to;

a first capacitance value related to said first, second, and third capacitors during a first time period,

a second capacitance value related to said first, second, and third capacitors during a second time period,

a third capacitance value related to said first, second, and third capacitors during a third time period, and

a fourth capacitance value during a fourth time period, said fourth capacitance value based on said first, second, and third capacitors;

acquire a first capacitance measurement of said first receiver path during said first time period, a second capacitance measurement of said first receiver path during said second time period, a third capacitance measurement of said first receiver path during said third time period, and a fourth capacitance measurement of said first receiver path during said fourth time period; and

determine a measurement of linearity of said first receiver path based on said first, second, third and fourth capacitance measurements of said first receiver path.

4. The input device of claim 1, wherein said processing system is further configured to:

selectively couple said second receiver path with said first capacitor;

acquire a measurement of a second resulting signal from at least one of said second receiver path or a third receiver path of said plurality of receiver paths while said second receiver path is coupled with said first capacitor and while said bypass switch is not bypassing said first capacitor; and

determine whether said second receiver path is ohmically coupled with said third receiver path based on said measurement of said second resulting signal.

5. The input device of claim 1, wherein said processing system is further configured to:

selectively configure said bypass switch to bypass said first capacitor;

drive a transmitter signal onto said first receiver path;

acquire a measurement of a second resulting signal on said second receiver path of said plurality of receiver paths while driving said transmitter signal through said bypass switch and onto said first receiver path and while said bypass switch is bypassing said first capacitor; and

determine whether an acceptable discontinuity exists in said first receiver path based on a comparison of said measurement of said second resulting signal to a defined value range.

6. The input device of claim 1, wherein said processing system is further configured to:

couple a first transmitter path of a plurality of transmitter paths with an electrical potential, wherein said processing system is coupled to said plurality of transmitter paths;

transmit with a second transmitter path of said plurality of transmitter paths while said first transmitter path is electrically floating;

selectively couple said first capacitor with said first receiver path;

acquire a measurement of a second resulting signal from said first receiver path while coupling said first transmitter path with said electrical potential and while transmitting with said second transmitter path; and

determine whether an ohmic coupling exists between said first transmitter path and said second transmitter path based on said measurement of said second resulting signal.

7. The input device of claim 1, wherein said processing system is further configured to:

bypass said first capacitor;

couple a first transmitter path of a plurality of transmitter paths with an electrical potential, wherein said processing system is coupled to said plurality of transmitter paths;

transmit with a second transmitter path of said plurality of transmitter paths while said first transmitter path is electrically floating;

acquire a measurement of a second resulting signal from said first receiver path while coupling said first transmitter path with said electrical potential and while transmitting with said second transmitter path; and

determine whether an acceptable discontinuity exists within said first transmitter path based on said measurement of said second resulting signal.

8. A processing system comprising:

a selection module configured for selectively bypassing a first capacitor and for selectively coupling one or more receiver paths of a plurality of receiver paths with said first capacitor;

a measurement acquirer configured for acquiring a measurement of a first resulting signal from at least one of a first receiver path or a second receiver path of said plurality of receiver paths while said first receiver path is coupled with said first capacitor and while said first capacitor is not bypassed; and

a continuity determiner configured for determining whether said first receiver path is ohmically coupled with said second receiver path based on said measurement of said first resulting signal.

9. The processing system of claim 8, further comprising a linearity determiner, and wherein:

said selection module is configured for selectively coupling one or more of said first capacitor, a second capacitor, and a third capacitor to said first receiver path such that;

a first capacitance value is coupled to said first receiver path during a first time period,

a second capacitance value is coupled to said first receiver path during a second time period,

a third capacitance value is coupled to said first receiver path during a third time period, and

a fourth capacitance is coupled to said first receiver path during a fourth time period, wherein said first, second, third, and fourth capacitance values are different;

said measurement acquirer is configured for acquiring a first measurement of capacitance of said first receiver path during said first time period, a second measurement of capacitance of said first receiver path during said second time period, a third measurement of capacitance of said first receiver path during said third time period, and a fourth measurement of capacitance of said first receiver path during said fourth time period; and

said linearity determiner is configured for determining a measurement of linearity of said first receiver path based on said first, second, third, and fourth measurements of capacitance of said first receiver path.

10. The processing system of claim 8, further comprising transmitter circuitry, wherein:

said transmitter circuitry is configured for driving a transmitter signal onto said first receiver path;

said measurement acquirer is further configured for acquiring a measurement of a second resulting signal on a second receiver path of said plurality of receiver paths while said transmitter signal is driven onto said first receiver path and while said first capacitor is bypassed; and

said continuity determiner is configured for determining whether an acceptable discontinuity exists in said first receiver path based on a comparison of said measurement of said second resulting signal to a defined value range.

11. The processing system of claim 10, wherein:

said transmitter circuitry is further configured for driving said transmitter signal onto said second receiver path;

said measurement acquirer is further configured for acquiring a measurement of a third resulting signal on a third receiver path of said plurality of receiver paths while said transmitter signal is driven by said transmitter circuitry onto said second receiver path and while said first capacitor is bypassed; and

said continuity determiner is further configured for determining whether an acceptable discontinuity exists in said second receiver path based on a comparison of said third resulting signal to said defined value range.

12. The processing system of claim 8, wherein said selection module is further configured for selectively coupling either or both of a second capacitor and a third capacitor to any of said plurality of receiver paths.

13. The processing system of claim 8, wherein said selection module is configured for selectively bypassing said first capacitor by selectively closing a bypass switch.

14. The processing system of claim 8, wherein:

said selection module is configured for selectively coupling said second receiver path with said first capacitor;

said measurement acquirer is further configured for acquiring a measurement of a second resulting signal from at least one of said second receiver path or a third receiver path of said plurality of receiver paths while said second receiver path is coupled with said first capacitor and while first capacitor is not bypassed; and

said continuity determiner is further configured for determining whether said second receiver path is ohmically coupled with said third receiver path based on said measurement of said second resulting signal.

15. A processing system comprising:

a selection module configured for selectively bypassing a first capacitor and for selectively coupling one or more receiver paths of a plurality receiver paths with said first capacitor;

transmitter circuitry configured for driving a transmitter signal onto a first receiver path of said plurality of receiver paths;

a measurement acquirer configured for acquiring a measurement of a first resulting signal on a second receiver path of said plurality of receiver paths while said transmitter circuitry is driving said transmitter signal onto said first receiver path and while said first capacitor is bypassed; and

a continuity determiner configured for determining whether an acceptable discontinuity exists in said first receiver path based on a comparison of said measurement of said first resulting signal to a defined value range.

16. The processing system of claim 15, wherein said selection module is further configured to selectively couple either or both of a second capacitor and a third capacitor to any of said plurality of receiver paths.

17. The processing system of claim 15, wherein:

said transmitter circuitry is further configured for driving said transmitter signal onto said second receiver path;

said measurement acquirer is further configured for acquiring a measurement of a second resulting signal on a third receiver path of said plurality of receiver paths while said transmitter circuitry is driving said transmitter signal onto said second receiver path and while said first capacitor is bypassed; and

said continuity determiner is further configured for determining whether an acceptable discontinuity exists in said second receiver path based on a comparison of said measurement of said second resulting signal to said defined value range.

18. The processing system of claim 15, further comprising a linearity determiner, wherein:

said selection module is configured for selectively coupling one or more of said first capacitor, a second capacitor, and a third capacitor to said first receiver path such that;

a first capacitance value is coupled to said first receiver path during a first time period,

a second capacitance value is coupled to said first receiver path during a second time period,

a third capacitance value is coupled to said first receiver path during a third time period, and

a fourth capacitance value is coupled to said first receiver path during a fourth time period, wherein said first, second, third, and fourth capacitance values are different;

said measurement acquirer is further configured for acquiring a first measurement of capacitance of said first receiver path during said first time period, a second measurement of capacitance of said first receiver path during said second time period, a third measurement of capacitance of said first receiver path during said third time period, and a fourth measurement of capacitance of said first receiver path during said fourth time period; and

said linearity determiner configured for determining a measurement of linearity of said first receiver path based on said first, second, third, and fourth measurements of capacitance of said first receiver path.

19. The processing system of claim 15, wherein said measurement acquirer is further configured for acquiring a measurement of a second resulting signal from at least one of said first receiver path and said second receiver path of said plurality of receiver paths while said first receiver path is coupled with said first capacitor and while said first capacitor is not bypassed;

and

said continuity determiner configured for determining whether said first receiver path is ohmically coupled with said second receiver path based on said measurement of said second resulting signal.

20. The processing system of claim 19, wherein said measurement acquirer is further configured for acquiring a measurement of a third resulting signal from at least one of said second receiver path and a third receiver path of said plurality of receiver paths while said second receiver path is coupled with said first capacitor and while said first capacitor is not bypassed;

and

said continuity determiner configured for determining whether said second receiver path is ohmically coupled with said third receiver path based on said measurement of said third resulting signal.