Method for evaluating semiconductor device

• US 8,686,750 B2
• Filed: 05/05/2011
• Issued: 04/01/2014
• Est. Priority Date: 05/13/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd., University of Central Florida Research Foundation Inc. (State University System of Florida)
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kamata, Koichiro
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US13/101,387
• Publication Number:
  US 20110279144A1
• Time in Patent Office: 1,062 Days
• Field of Search: None
• US Class Current: 324/762.09
• CPC Class Codes: G01R 31/2619 for measuring thermal properties thereof

Abstract

To provide a simple method for evaluating reliability of a transistor, a simple test which correlates with a bias-temperature stress test (BT test) is performed instead of the BT test. Specifically, a gate current value is measured in the state where a voltage lower than the threshold voltage of an n-channel transistor whose channel region includes an oxide semiconductor is applied between a gate and a source of the transistor and a potential applied to a drain is higher than a potential applied to the gate. The evaluation of the gate current value can be simply performed compared to the case where the BT test is performed; for example, it takes short time to measure the gate current value. That is, reliability of a semiconductor device including the transistor can be easily evaluated.

Claims

1. A method for evaluating a semiconductor device, comprising the steps of:

measuring a gate current value in a state where a voltage lower than a threshold voltage of an n-channel transistor whose channel region comprises an oxide semiconductor is applied between a gate and a source of the transistor, and a potential applied to a drain is higher than a potential applied to the gate; and

evaluating reliability of the semiconductor device comprising the transistor, using the gate current value.

2. The method for evaluating a semiconductor device, according to claim 1, wherein the voltage between the gate and the source of the transistor is negative.

3. The method for evaluating a semiconductor device, according to claim 1, wherein the potential applied to the drain is zero.

4. A method for evaluating a semiconductor device, comprising the steps of:

measuring a variation in a gate current value with time in a state where a voltage lower than a threshold voltage of an n-channel transistor whose channel region comprises an oxide semiconductor is applied between a gate and a source of the transistor, and a potential applied to a drain is higher than a potential applied to the gate; and

evaluating reliability of the semiconductor device, comprising the transistor, using the variation in the gate current value with time.

5. The method for evaluating a semiconductor device, according to claim 4, wherein the voltage between the gate and the source of the transistor is negative.

6. The method for evaluating a semiconductor device, according to claim 4, wherein the potential applied to the drain is zero.